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  8 bit microcontroller tlcs-870/c series TMP86FH09AMG
? 2011 toshiba corporation all rights reserved
revision history date revision comment 2010/10/5 tentative 1 first release of tentative 2010/10/14 tentative 2 contents revised 2010/11/25 tentative 3 contents revised 2010/12/8 tentative 4 contents revised 2011/2/24 tentative 5 contents revised 2011/4/8 1 first release

table of contents TMP86FH09AMG 1.1 features......................................................................................................................................1 1.2 pin assignment..........................................................................................................................3 1.3 block diagram........................................................................................................................... 4 1.4 pin names and functions ..........................................................................................................5 2. operational description 2.1 cpu core functions ................................................................................................................ 7 2.1.1 memory address map ....................................................................................................................................................... 7 2.1.2 program memory (flash) ................................................................................................................................................... 7 2.1.3 data memory ( ram) ......................................................................................................................................................... 7 2.2 system clock controller .......................................................................................................... 8 2.2.1 clock generator ................................................................................................................................................................. 8 2.2.2 timing generator ............................................................................................................................................................. 10 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit ...................................................................................................................................... 11 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control .................................................................................................................................................. 16 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit ........................................................................................................................... 29 2.3.1 external reset input ......................................................................................................................................................... 29 2.3.2 address trap reset ............................................................................................................................................................. 30 2.3.3 watchdog timer reset ....................................................................................................................................................... 30 2.3.4 system clock reset ............................................................................................................................................................ 30 3. interrupt control circuit 3.1 interrupt latches ( il15 to il2) ............................................................................................... 31 3.2 interrupt enable register ( eir) ............................................................................................... 32 3.2.1 interrupt master enable flag ( imf) .................................................................................................................................. 32 3.2.2 individual interrupt enable flags (ef15 to ef4) ............................................................................................................. 32 3.3 interrupt source selector ( intsel)....................................................................................... 34 3.4 interrupt sequence ................................................................................................................ 34 3.4.1 interrupt acceptance processing is packaged as follows. ................................................................................................ 34 3.4.2 saving/restoring general-purpose registers ...................................................................................................................... 35 3.4.2.1 using push and pop instructions 3.4.2.2 using data transfer instructions 3.4.3 interrupt return ................................................................................................................................................................. 36 3.5 software interrupt ( intsw) .................................................................................................. 37 3.5.1 address error detection .................................................................................................................................................... 37 3.5.2 debugging ........................................................................................................................................................................ 38 3.6 undefined instruction interrupt ( intundef) ...................................................................... 38 i
3.7 address trap interrupt ( intatrap) ................................................................................... 38 3.8 external interrupts .................................................................................................................. 38 4. special function register ( sfr) 4.1 sfr.......................................................................................................................................... 41 4.2 dbr......................................................................................................................................... 43 5. i/o ports 5.1 p0 ( p07 to p00) port ( high current) ..................................................................................... 46 5.2 p1 ( p16 to p10) port .............................................................................................................. 47 5.3 p2 ( p22 to p20) port .............................................................................................................. 48 5.4 p3 ( p37 to p30) port............................................................................................................... 49 6. time base timer (tbt) 6.1 time base timer..................................................................................................................... 51 6.1.1 configuration.....................................................................................................................................................................51 6.1.2 control............................................................................................................................................................................... 51 6.1.3 function............................................................................................................................................................................. 52 6.2 divider output ( dvo)............................................................................................................ 53 6.2.1 configuration..................................................................................................................................................................... 53 6.2.2 control ............................................................................................................................................................................... 53 7. watchdog timer ( wdt) 7.1 watchdog timer configuration ............................................................................................. 55 7.2 watchdog timer control ....................................................................................................... 56 7.2.1 malfunction detection methods using the watchdog timer ......................................................................................... 56 7.2.2 watchdog timer enable .................................................................................................................................................. 57 7.2.3 watchdog timer disable ................................................................................................................................................. 58 7.2.4 watchdog timer interrupt ( intwdt) ............................................................................................................................58 7.2.5 watchdog timer reset ..................................................................................................................................................... 59 7.3 address trap .......................................................................................................................... 60 7.3.1 selection of address trap in internal ram ( atas) ..................................................................................................... 60 7.3.2 selection of operation at address trap ( atout) .........................................................................................................60 7.3.3 address trap interrupt ( intatrap)............................................................................................................................... 60 7.3.4 address trap reset........................................................................................................................................................... 61 8. 16-bit timer/counter 1 ( tc1) 8.1 configuration........................................................................................................................... 63 8.2 timer/counter control............................................................................................................ 64 8.3 function................................................................................................................................... 66 8.3.1 timer mode........................................................................................................................................................................ 66 8.3.2 external trigger timer mode ........................................................................................................................................... 68 8.3.3 event counter mode......................................................................................................................................................... 70 8.3.4 window mode................................................................................................................................................................... 71 8.3.5 pulse width measurement mode...................................................................................................................................... 72 8.3.6 programmable pulse generate ( ppg) output mode........................................................................................................ 75 ii
9. 8-bit timercounter ( tc3, tc4) 9.1 configuration ..........................................................................................................................79 9.2 timercounter control............................................................................................................. 80 9.3 function................................................................................................................................... 85 9.3.1 8-bit timer mode ( tc3 and 4)........................................................................................................................................ 85 9.3.2 8-bit event counter mode ( tc3, 4).................................................................................................................................86 9.3.3 8-bit programmable divider output ( pdo) mode ( tc3, 4)...........................................................................................86 9.3.4 8-bit pulse width modulation ( pwm) output mode ( tc3, 4)...................................................................................... 89 9.3.5 16-bit timer mode ( tc3 and 4)...................................................................................................................................... 91 9.3.6 16-bit event counter mode ( tc3 and 4)......................................................................................................................... 92 9.3.7 16-bit pulse width modulation ( pwm) output mode ( tc3 and 4).............................................................................. 92 9.3.8 16-bit programmable pulse generate ( ppg) output mode ( tc3 and 4)....................................................................... 95 9.3.9 warm-up counter mode...................................................................................................................................................97 9.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 9.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 10. asynchronous serial interface ( uart) 10.1 configuration ........................................................................................................................99 10.2 control ................................................................................................................................ 100 10.3 transfer data format.......................................................................................................... 103 10.4 transfer rate....................................................................................................................... 104 10.5 data sampling method........................................................................................................ 104 10.6 stop bit length................................................................................................................. 105 10.7 parity.................................................................................................................................... 105 10.8 transmit/receive operation................................................................................................105 10.8.1 data transmit operation............................................................................................................................................... 105 10.8.2 data receive operation................................................................................................................................................. 105 10.9 status flag........................................................................................................................... 106 10.9.1 parity error.................................................................................................................................................................... 106 10.9.2 framing error................................................................................................................................................................ 106 10.9.3 overrun error................................................................................................................................................................ 106 10.9.4 receive data buffer full.............................................................................................................................................. 107 10.9.5 transmit data buffer empty......................................................................................................................................... 107 10.9.6 transmit end flag......................................................................................................................................................... 108 11. serial expansion interface ( sei) 11.1 features ............................................................................................................................... 109 11.2 sei registers ...................................................................................................................... 110 11.2.1 sei control register (secr) ....................................................................................................................................... 110 11.2.1.1 transfer rate 11.2.2 sei status register ( sesr).......................................................................................................................................... 111 11.2.3 sei data register ( sedr)............................................................................................................................................ 111 11.3 sei operation ..................................................................................................................... 112 11.3.1 controlling sei clock polarity and phase .................................................................................................................... 112 11.3.2 sei data and clock timing ............................................................................................................................................112 11.4 sei pin functions ...............................................................................................................113 11.4.1 sclk pin ...................................................................................................................................................................... 113 11.4.2 miso/mosi pins ......................................................................................................................................................... 113 11.4.3 ss pin ........................................................................................................................................................................... 113 iii
11.5 sei transfer formats ......................................................................................................... 114 11.5.1 cpha (secr register bit 2) = 0 format ..................................................................................................................... 114 11.5.2 cpha = 1 format ......................................................................................................................................................... 114 11.6 functional description........................................................................................................ 116 11.7 interrupt generation ........................................................................................................... 117 11.8 sei system errors .............................................................................................................. 117 11.8.1 write collision error...................................................................................................................................................... 117 11.8.2 overflow error .............................................................................................................................................................. 117 11.9 bus driver protection ......................................................................................................... 118 12. 10-bit ad converter ( adc) 12.1 configuration ...................................................................................................................... 119 12.2 register configuration......................................................................................................... 120 12.3 function .............................................................................................................................. 123 12.3.1 software start mode...................................................................................................................................................... 123 12.3.2 repeat mode.................................................................................................................................................................. 123 12.3.3 register setting............................................................................................................................................................ 124 12.4 stop/slow modes during ad conversion..................................................................... 125 12.5 analog input voltage and ad conversion result............................................................. 126 12.6 precautions about ad converter........................................................................................ 127 12.6.1 analog input pin voltage range..................................................................................................................................... 127 12.6.2 analog input shared pins............................................................................................................................................... 127 12.6.3 noise countermeasure................................................................................................................................................... 127 13. key-on wakeup (kwu) 13.1 configuration....................................................................................................................... 129 13.2 control................................................................................................................................. 130 14. flash memory 14.1 flash memory control........................................................................................................ 132 14.1.1 flash memory command sequence execution control ( flscr)............................................................ 132 14.1.2 flash memory standby control ( flsstb).................................................................................................... 132 14.2 command sequence............................................................................................................ 134 14.2.1 byte program................................................................................................................................................................. 134 14.2.2 sector erase ( 4-kbyte erase) ......................................................................................................................................... 134 14.2.3 chip erase ( all erase) .................................................................................................................................................. 135 14.2.4 product id entry........................................................................................................................................................... 135 14.2.5 product id exit.............................................................................................................................................................. 135 14.2.6 security program........................................................................................................................................................... 135 14.3 toggle bit ( d6)................................................................................................................... 136 14.4 access to the flash memory area...................................................................................... 137 14.4.1 flash memory control in the serial prom mode...................................................................................................... 137 14.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) 14.4.2 flash memory control in the mcu mode................................................................................................................... 139 14.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) 15. serial prom mode iv
15.1 outline................................................................................................................................. 141 15.2 memory mapping................................................................................................................ 141 15.3 serial prom mode setting................................................................................................ 142 15.3.1 serial prom mode control pins................................................................................................................................. 142 15.3.2 pin function................................................................................................................................................................... 142 15.3.3 example connection for on-board writing................................................................................................................. 143 15.3.4 activating the serial prom mode...............................................................................................................................144 15.4 interface specifications for uart..................................................................................... 145 15.5 operation command........................................................................................................... 146 15.6 operation mode................................................................................................................... 146 15.6.1 flash memory erasing mode ( operating command: f0h)......................................................................................... 148 15.6.2 flash memory writing mode ( operation command: 30h)......................................................................................... 150 15.6.3 ram loader mode ( operation command: 60h)........................................................................................................ 153 15.6.4 flash memory sum output mode ( operation command: 90h)................................................................................ 155 15.6.5 product id code output mode ( operation command: c0h)..................................................................................... 156 15.6.6 flash memory status output mode ( operation command: c3h).............................................................................. 158 15.6.7 flash memory security program setting mode ( operation command: fah)............................................................ 160 15.7 error code........................................................................................................................... 162 15.8 checksum ( sum)................................................................................................................ 162 15.8.1 calculation method....................................................................................................................................................... 162 15.8.2 calculation data............................................................................................................................................................. 163 15.9 intel hex format ( binary)...................................................................................................164 15.10 passwords.......................................................................................................................... 164 15.10.1 password string...........................................................................................................................................................165 15.10.2 handling of password error........................................................................................................................................165 15.10.3 password management during program development.............................................................................................. 165 15.11 product id code................................................................................................................166 15.12 flash memory status code............................................................................................... 166 15.13 specifying the erasure area.............................................................................................. 168 15.14 port input control register............................................................................................... 168 15.15 flowchart........................................................................................................................... 170 15.16 uart timing................................................................................................................... 171 16. input/output circuitry 16.1 control pins......................................................................................................................... 173 16.2 input/output ports............................................................................................................... 174 17. electrical characteristics 17.1 absolute maximum ratings................................................................................................ 177 17.2 operating conditions........................................................................................................... 178 17.2.1 mcu mode (flash programming or erasing) ..............................................................................................................178 17.2.2 mcu mode ( except flash programming or erasing) ................................................................................................. 178 17.2.3 serial prom mode....................................................................................................................................................... 179 17.3 dc characteristics .............................................................................................................. 180 17.4 ad characteristics............................................................................................................... 181 17.5 ac characteristics............................................................................................................... 182 17.6 flash characteristics............................................................................................................182 17.6.1 write/erase characteristics........................................................................................................................................... 182 17.7 oscillating conditions......................................................................................................... 183 17.8 handling precaution............................................................................................................ 183 v
18. package dimensions vi
cmos 8-bit microcontroller TMP86FH09AMG the TMP86FH09AMG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of flash memory. product no. rom (flash) ram package emulation chip TMP86FH09AMG 16384 bytes 512 bytes p-sop32-380-1.27 tmp86c909xbg 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 17interrupt sources (external : 5 internal : 12) 3. input / output ports (26 pins) 4. prescaler - time base timer - divider output function 5. watchdog timer 6. 16-bit timer counter: 1 ch - timer, external trigger, window, pulse width measurement, event counter, programmable pulse generate (ppg) modes 7. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg), 16bit mode (8bit timer 2ch combination) modes 8. 8-bit uart : 1 ch 9. 8bit serial expansion interface (sei): 1 channel (msb/lsb selectable and max. 4mbps at 16mhz) 10. 10-bit successive approximation type ad converter this product uses the super flash? technology under the licence of silicon storage technology, inc. super flash? is registered trademark of sili- con storage technology, inc. TMP86FH09AMG page 1
- analog input: 6 ch 11. key-on wakeup : 4 channels 12. clock operation single clock mode dual clock mode 13. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation using low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation using low-frequency clock.(high-frequency clock os- cillate.) idle0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using high fre- quency clock. release by falling edge of the source clock which is set by tbtcr. idle1 mode: cpu stops and peripherals operate using high frequency clock. release by interruputs (cpu restarts). idle2 mode: cpu stops and peripherals operate using high and low frequency clock. release by inter- ruputs. (cpu restarts). sleep0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using low fre- quency clock.release by falling edge of the source clock which is set by tbtcr. sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interruput. (cpu restarts). sleep2 mode: cpu stops and peripherals operate using high and low frequency clock. release by inter- ruput. 14. wide operation voltage: 4.5 v to 5.5 v at 16mhz /32.768 khz 2.7 v to 5.5 v at 8 mhz /32.768 khz TMP86FH09AMG 1.1 features page 2
1.2 pin assignment vss p37 (ain5/stop5) xin p36 (ain4/stop4) xout p35 (ain3/stop3) test p34 (ain2/stop2) vdd p33 (ain1) (xtin) p21 p32 (ain0) (xtout) p22 p31 (tc4/ pdo4/pwm4/ppg4) reset p30 (tc3/ pdo3/pwm3) ( stop/ int5) p20 p12 ( dvo) (txd) p00 p11 (int1) (rxd) p01 p10 ( int0) (rxd0/boot/sclk) p02 p07 (tc1/int4) (txd0/mosi) p03 p06 (int3/ ppg) (miso) p04 p05 ( ss) p14 p13 p16 p15 figure 1-1 pin assignment TMP86FH09AMG page 3
1.3 block diagram figure 1-2 block diagram TMP86FH09AMG 1.3 block diagram page 4
1.4 pin names and functions the TMP86FH09AMG has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/2) pin name pin number input/output functions p07 tc1 int4 21 io i i port07 tc1 input external interrupt 4 input p06 int3 ppg 20 io i o port06 external interrupt 3 input ppg output p05 ss 19 io i port05 sei master/slave select input p04 miso 14 io io port04 sei master input, slave output p03 mosi txd0 13 io io o port03 sei master output, slave input uart data output 0 p02 sclk boot rxd0 12 io io i i port02 sei serial clock input/output pin serial prom mode control input uart data input 0 p01 rxd 11 io i port01 uart data input p00 txd 10 io o port00 uart data output p16 16 io port16 p15 17 io port15 p14 15 io port14 p13 18 io port13 p12 dvo 24 io o port12 divider output p11 int1 23 io i port11 external interrupt 1 input p10 int0 22 io i port10 external interrupt 0 input p22 xtout 7 io o port22 resonator connecting pins(32.768khz) for inputting exter- nal clock p21 xtin 6 io i port21 resonator connecting pins(32.768khz) for inputting exter- nal clock p20 int5 stop 9 io i i port20 external interrupt 5 input stop mode release signal input TMP86FH09AMG page 5
table 1-1 pin names and functions(2/2) pin name pin number input/output functions p37 ain5 stop5 32 io i i port37 analog input5 stop5 p36 ain4 stop4 31 io i i port36 analog input4 stop4 p35 ain3 stop3 30 io i i port35 analog input3 stop3 p34 ain2 stop2 29 io i i port34 analog input2 stop2 p33 ain1 28 io i port33 analog input1 p32 ain0 27 io i port32 analog input0 p31 tc4 pdo4/pwm4/ppg4 26 io i o port31 tc4 input pdo4/pwm4/ppg4 output p30 tc3 pdo3/pwm3 25 io i o port30 tc3 input pdo3/pwm3 output xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. vdd 5 i power supply vss 1 i 0(gnd) TMP86FH09AMG 1.4 pin names and functions page 6
2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system clock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FH09AMG memory is composed flash, ram, dbr(data buffer register) and sfr(special func- tion register). they are all mapped in 64-kbyte address space. figure 2-1 shows the TMP86FH09AMG mem- ory address map. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 512 bytes 023f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers 0fff h c000 h flash: program memory flash 16384 bytes ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FH09AMG has a 16384 bytes (address c000h to ffffh) of program memory (flash). 2.1.3 data memory (ram) the TMP86FH09AMG has 512bytes (address 0040h to 023fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ram are located in the direct area; instructions with shorten operations are available against such an area. TMP86FH09AMG page 7
the data memory contents become unstable when the power supply is turned on; therefore, the data memo- ry should be initialized by an initialization routine. example :clears ram to 00h. (TMP86FH09AMG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 01ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers figure 2-2 system clock control 2.2.1 clock generator the clock generator generates the basic clock which provides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-pow- er operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resona- tor between the xin/xout and xtin/xtout pins respectively. clock input from an external oscillator is al- so possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. TMP86FH09AMG 2. operational description 2.2 system clock controller page 8
xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitor- ing the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscillation frequency should create the program for the ad- justment in advance. TMP86FH09AMG page 9
2.2.2 timing generator the timing generator generates the various system clocks supplied to the cpu core and peripheral hard- ware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 and tbtcr, that is shown in figure 2-4. as reset and stop mode started/canceled, the prescaler and the divider are cleared to 0. multi- plexer high-frequency clock fc low-frequency clock fs divider sysck fc/4 fc or fs machine cycle counters main system clock generator 1 2 1 4 3 2 8 7 10 9 12 11 14 13 16 15 dv7ck multiplexer warm-up controller watchdog timer a s b y s b0 a0 y0 b1 a1 y1 5 6 17 18 19 20 21 timer counter, serial interface, time-base-timer, divider output, etc. (peripheral functions) figure 2-4 configuration of timing generator TMP86FH09AMG 2. operational description 2.2 system clock controller page 10
timing generator control register tbtcr (0036h) 7 6 5 4 3 2 1 0 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w note 1: in single clock mode, do not set dv7ck to 1. note 2: do not set 1 on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *: dont care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv7ck setting is ineffective during the warm-up period af- ter release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operation are synchronized with the main system clock. the minimum instruction execution unit is called an machine cycle. there are a total of 10 different types of instructions for the tlcs-870/c series: ranging from 1-cycle instructions which require one ma- chine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. a ma- chine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s] figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-fre- quency clocks, and switches the main system clock. there are three operating modes: single clock mode, du- al clock mode and stop mode. these modes are controlled by the system control registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequency clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports. the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip peripherals operate using the high-frequency clock. the TMP86FH09AMG is placed in this mode after reset. TMP86FH09AMG page 11
(2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are hal- ted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 = "1", and idle1 mode is released to normal1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. when the imf (interrupt master enable flag) is 1 (interrupt enable), the execution will resume with the accept- ance of the interrupt, and the operation will return to normal after the interrupt service is completed. when the imf is 0 (interrupt disable), the execution will resume with the instruction which fol- lows the idle1 mode start instruction. (3) idle0 mode in this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. this mode is enabled by syscr2 = "1". when idle0 mode starts, the cpu stops and the timing generator stops feeding the clock to the pe- ripheral circuits other than tbt. then, upon detecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to all peripheral circuits. when returned from idle0 mode, the cpu restarts operating, entering normal1 mode back again. idle0 mode is entered and returned regardless of how tbtcr is set. when imf = 1, ef6 (tbt interrupt individual enable flag) = 1, and tbtcr = 1, interrupt pro- cessing is performed. when idle0 mode is entered while tbtcr = 1, the inttbt in- terrupt latch is set after returning to normal1 mode. 2.2.3.2 dual-clock mode both the high-frequency and low-frequency oscillation circuits are used in this mode. p21 (xtin) and p22 (xtout) pins cannot be used as input/output ports. the main system clock is obtained from the high- frequency clock in normal2 and idle2 modes, and is obtained from the low-frequency clock in slow and sleep modes. the machine cycle time is 4/fc [s] in the normal2 and idle2 modes, and 4/fs [s] (122 s at fs = 32.768 khz) in the slow and sleep modes. the tlcs-870/c is placed in the single-clock mode during reset. to use the dual-clock mode, the low- frequency oscillator should be turned on at the start of a program. (1) normal2 mode in this mode, the cpu core operates with the high-frequency clock. on-chip peripherals operate us- ing the high-frequency clock and/or low-frequency clock. (2) slow2 mode in this mode, the cpu core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. as the syscr2 becomes "1", the hard- ware changes into slow2 mode. as the syscr2 becomes 0, the hardware changes in- to normal2 mode. as the syscr2 becomes 0, the hardware changes into slow1 mode. do not clear syscr2 to 0 during slow2 mode. (3) slow1 mode this mode can be used to reduce power-consumption by turning off oscillation of the high-frequen- cy clock. the cpu core and on-chip peripherals operate using the low-frequency clock. TMP86FH09AMG 2. operational description 2.2 system clock controller page 12
switching back and forth between slow1 and slow2 modes are performed by syscr2. in slow1 and sleep modes, the input clock to the 1st stage of the divider is stop- ped; output from the 1st to 6th stages is also stopped. (4) idle2 mode in this mode, the internal oscillation circuit remain active. the cpu and the watchdog timer are hal- ted; however, on-chip peripherals remain active (operate using the high-frequency clock and/or the low-frequency clock). starting and releasing of idle2 mode are the same as for idle1 mode, ex- cept that operation returns to normal2 mode. (5) sleep1 mode in this mode, the internal oscillation circuit of the low-frequency clock remains active. the cpu, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; howev- er, on-chip peripherals remain active (operate using the low-frequency clock). starting and releas- ing of sleep mode are the same as for idle1 mode, except that operation returns to slow1 mode. in slow1 and sleep1 modes, the input clock to the 1st stage of the divider is stopped; out- put from the 1st to 6th stages is also stopped. (6) sleep2 mode the sleep2 mode is the idle mode corresponding to the slow2 mode. the status under the sleep2 mode is same as that under the sleep1 mode, except for the oscillation circuit of the high- frequency clock. (7) sleep0 mode in this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. this mode is enabled by setting 1 on bit syscr2. when sleep0 mode starts, the cpu stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon detecting the falling edge of the source clock selec- ted with tbtcr, the timing generator starts feeding the clock to all peripheral circuits. when returned from sleep0 mode, the cpu restarts operating, entering slow1 mode back again. sleep0 mode is entered and returned regardless of how tbtcr is set. when imf = 1, ef6 (tbt interrupt individual enable flag) = 1, and tbtcr = 1, inter- rupt processing is performed. when sleep0 mode is entered while tbtcr = 1, the inttbt interrupt latch is set after returning to slow1 mode. 2.2.3.3 stop mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with a lowest power consumption during stop mode. stop mode is started by the system control register 1 (syscr1), and stop mode is released by a input- ting (either level-sensitive or edge-sensitive can be programmable selected) to the stop pin. after the warm-up period is completed, the execution resumes with the instruction which follows the stop mode start instruction. TMP86FH09AMG page 13
note 2 syscr2 = "1" stop pin input stop pin input stop pin input interrupt interrupt syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "0" syscr1 = "1" syscr1 = "1" syscr1 = "1" syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" reset release normal1 mode idle0 mode (a) single-clock mode idle1 mode normal2 mode idle2 mode syscr2 = "1" slow2 mode sleep2 mode slow1 mode sleep1 mode sleep0 mode reset (b) dual-clock mode stop syscr2 = "1" note 2 note 1: normal1 and normal2 modes are generically called normal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by falling edge of tbtcr setting. figure 2-6 operating mode transition diagram table 2-1 operating mode and conditions operating mode oscillator cpu core wdt tbt ad converter other peripherals machine cy- cle time high frequency low frequency single clock reset oscillation stop reset reset reset reset reset 4/fc [s] normal1 operate operate operate operate operate idle1 halt halt idle0 halt halt stop stop halt - dual clock normal2 oscillation oscillation operate with high-freq. operate with high or low- freq. operate operate operate 4/fc [s] idle2 halt halt slow2 operate with low-freq. operate with low-freq. halt 4/fs [s] sleep2 halt halt slow1 stop operate with low-freq. operate with low-freq. sleep1 halt halt sleep0 halt stop stop halt halt - TMP86FH09AMG 2. operational description 2.2 system clock controller page 14
system control register 1 syscr1 7 6 5 4 3 2 1 0 (0038h) stop relm retm outen wut (initial value: 0000 00**) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) r/w relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release r/w retm operating mode after stop mode 0: return to normal1/2 mode 1: return to slow1 mode r/w outen port output during stop mode 0: high impedance 1: output kept r/w wut warm-up time at releasing stop mode return to normal mode return to slow mode r/w 00 01 10 11 3 x 2 16 /fc 2 16 /fc 3 x 2 14 /fc 2 14 /fc 3 x 2 13 /fs 2 13 /fs 3 x 2 6 /fs 2 6 /fs note 1: always set retm to 0 when transiting from normal mode to stop mode. always set retm to 1 when transit- ing from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *; dont care note 4: bits 0 and 1 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = 0, input value is fixed to 0; therefore it may cause exter- nal interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: in case of setting as stop mode is released by a rising edge of stop pin input, the release setting by stop5 to stop2 on stopcr register is prohibited. note 8: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 be- comes high-z mode. note 9: the warming-up time should be set correctly for using oscillator. system control register 2 syscr2 (0039h) 7 6 5 4 3 2 1 0 xen xten sysck idle tghalt (initial value: 1000 *0**) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation r/w xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/ main system clock monitor (read) 0: high-frequency clock (normal1/normal2/idle1/idle2) 1: low-frequency clock (slow1/slow2/sleep1/sleep2) idle cpu and watchdog timer con- trol (idle1/2 and sleep1/2 modes) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1/2 and sleep1/2 modes) r/w tghalt tg control (idle0 and sleep0 modes) 0: feeding clock to all peripherals from tg 1: stop feeding clock to peripherals except tbt from tg. (start idle0 and sleep0 modes) note 1: a reset is applied if both xen and xten are cleared to 0, xen is cleared to 0 when sysck = 0, or xten is cleared to 0 when sysck = 1. note 2: *: dont care, tg: timing generator note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to 1 simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow1 is executed by the asynchronous internal clock, the pe- riod of idle0/sleep0 mode might be shorter than the period setting by tbtcr. TMP86FH09AMG page 15
note 6: when idle1/2 or sleep1/2 mode is released, idle is automatically cleared to 0. note 7: when idle0 or sleep0 mode is released, tghalt is automatically cleared to 0. note 8: before setting tghalt to 1, be sure to stop peripherals. if peripherals are not stopped, the interrupt latch of periph- erals may be set after idle0 or sleep0 mode is released. 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup in- put (stop5 to stop2) which are controlled by the stop mode release control register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 to 1. during stop mode, the following status is maintained. 1. oscillations are turned off, and all internal operations are halted. 2. the data memory, registers, the program status word and port output latches are all held in the status in effect before stop mode was entered. 3. the prescaler and the divider of the timing generator are cleared to 0. 4. the program counter holds the address 2 ahead of the instruction (e.g., [set (syscr1).7]) which started stop mode. stop mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selec- ted with the syscr1. do not use any key-on wakeup input (stop5 to stop2) for releasing stop mode in edge-sensitive mode. note 1: the stop mode can be released by either the stop or key-on wakeup pins (stop5 to stop2). how- ever, because the stop pin is different from the key-on wakeup and can not inhibit the release in- put, the stop pin must be used for releasing stop mode. note 2: during stop period (from start of stop mode to end of warm up), due to changes in the external in- terrupt pin signal, interrupt latches may be set to 1 and interrupts may be accepted immediately af- ter stop mode is released. before starting stop mode, therefore, disable interrupts. also, before en- abling interrupts after stop mode is released, clear unnecessary interrupt latches. (1) level-sensitive release mode (relm = 1) in this mode, stop mode is released by setting the stop pin high or detecting high or low edge input for the stop5 to stop2 pins which are enabled by stopcr. this mode is used for capaci- tor backup when the main power supply is cut off and long term battery backup. even if an instruction for starting stop mode is executed while stop pin input is high, stop mode does not start but instead the warm-up sequence starts immediately. thus, to start stop mode in the level-sensitive release mode, it is necessary for the program to first confirm that the stop pin input is low. the following two methods can be used for confirmation. 1. testing a port. 2. using an external interrupt input int5 ( int5 is a falling edge-sensitive input). TMP86FH09AMG 2. operational description 2.2 system clock controller page 16
example 1 :starting stop mode from normal mode by testing a port p20. ld (syscr1), 01010000b ; sets up the level-sensitive release mode sstoph: test (p2prd). 0 ; wait until the stop pin input goes low level jrs f, sstoph di ; imf 0 set (syscr1). 7 ; starts stop mode example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation figure 2-7 level-sensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = 0) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short program is executed repeatedly at periodic intervals. this periodic sig- nal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop5 to stop2 pin inputs for releasing stop mode in edge-sensitive release mode. example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode TMP86FH09AMG page 17
normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin figure 2-8 edge-sensitive release mode stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low-fre- quency clock oscillators are turned on; when returning to slow1 mode, only the low-fre- quency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all inter- nal operations remain halted. four different warm-up times can be selected with the syscr1 in accordance with the resonator characteristics. 3. when the warm-up time has elapsed, normal operation resumes with the instruction follow- ing the stop mode start instruction. note 1: when the stop mode is released, the start is made after the prescaler and the divider of the tim- ing generator are cleared to "0". note 2: stop mode can also be released by inputting low level on the reset pin, which immediately performs the normal reset operation. note 3: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be h level, rising together with the power supply volt- age. in this case, if an external time constant circuit has been connected, the reset pin in- put voltage will increase at a slower pace than the power supply voltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-in- verting high-level input voltage (hysteresis input). table 2-2 warm-up time example (at fc = 16.0 mhz, fs = 32.768 khz) wut warm-up time [ms] return to normal mode return to slow mode 00 01 10 11 12.288 4.096 3.072 1.024 750 250 5.85 1.95 note 1: the warm-up time is obtained by dividing the basic clock by the divider. therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when stop mode is released. thus, the warm-up time must be considered as an approximate value. TMP86FH09AMG 2. operational description 2.2 system clock controller page 18
instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock figure 2-9 stop mode start/release TMP86FH09AMG page 19
2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maska- ble interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to op- erate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of the instruction which starts these modes. reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction figure 2-10 idle1/2 and sleep1/2 modes TMP86FH09AMG 2. operational description 2.2 system clock controller page 20
? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual interrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sleep1/2 modes, set syscr2 to 1. ? release the idle1/2 and sleep1/2 modes idle1/2 and sleep1/2 modes include a normal release mode and an interrupt release mode. these modes are selected by interrupt master enable flag (imf). after releasing idle1/2 and sleep1/2 modes, the syscr2 is automatically cleared to 0 and the op- eration mode is returned to the mode preceding idle1/2 and sleep1/2 modes. idle1/2 and sleep1/2 modes can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. (1) normal release mode (imf = 0) idle1/2 and sleep1/2 modes are released by any interrupt source enabled by the individual inter- rupt enable flag (ef). after the interrupt is generated, the program operation is resumed from the in- struction following the idle1/2 and sleep1/2 modes start instruction. normally, the interrupt latch- es (il) of the interrupt source used for releasing must be cleared to 0 by load instructions. (2) interrupt release mode (imf = 1) idle1/2 and sleep1/2 modes are released by any interrupt source enabled with the individual in- terrupt enable flag (ef) and the interrupt processing is started. after the interrupt is processed, the pro- gram operation is resumed from the instruction following the instruction, which starts idle1/2 and sleep1/2 modes. note:when a watchdog timer interrupts is generated immediately before idle1/2 and sleep1/2 modes are started, the watchdog timer interrupt will be processed but idle1/2 and sleep1/2 modes will not be started. TMP86FH09AMG page 21
halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: starting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release figure 2-11 idle1/2 and sleep1/2 modes start/release TMP86FH09AMG 2. operational description 2.2 system clock controller page 22
2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following status is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instruction which starts idle0 and sleep0 modes. note:before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr = "1" interrupt processing imf = "1" yes tbt interrupt enable no no no no stopping peripherals by instruction yes starting idle0, sleep0 modes by instruction execution of the instruction which follows the idle0, sleep0 modes start instruction figure 2-12 idle0 and sleep0 modes TMP86FH09AMG page 23
? start the idle0 and sleep0 mode s stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 mode s, set syscr2 to 1. ? release the idle0 and sleep0 mode s idle0 and sleep0 mode s include a normal release mode and an interrupt release mode. these modes are selected by interrupt master flag (imf), the individual interrupt enable flag of tbt and tbtcr. after releasing idle0 and sleep0 mode s, the syscr2 is automatically cleared to 0 and the operation mode is returned to the mode preceding idle0 and sleep0 mode s. before starting the idle0 or sleep0 mode, when the tbtcr is set to 1, inttbt interrupt latch is set to 1. idle0 and sleep0 mode s can also be released by inputting low level on the reset pin. af- ter releasing reset, the operation mode is started from normal1 mode. note:idle0 and sleep0 mode s start/release without reference to tbtcr setting. (1) normal release mode (imf ?ef6? tbtcr = 0) idle0 and sleep0 mode s are released by the source clock falling edge, which is setting by the tbtcr. after the falling edge is detected, the program operation is resumed from the in- struction following the idle0 and sleep0 mode s start instruction. before starting the idle0 or sleep0 mode, when the tbtcr is set to 1, inttbt interrupt latch is set to 1. (2) interrupt release mode (imf ?ef6? tbtcr = 1) idle0 and sleep0 mode s are released by the source clock falling edge, which is setting by the tbtcr and inttbt interrupt processing is started. note 1: because returning from idle0, sleep0 to normal1, slow1 is executed by the asynchro- nous internal clock, the period of idle0, sleep0 mode might be the shorter than the period set- ting by tbtcr. note 2: when a watchdog timer interrupt is generated immediately before idle0/sleep0 mode is star- ted, the watchdog timer interrupt will be processed but idle0/sleep0 mode will not be started. TMP86FH09AMG 2. operational description 2.2 system clock controller page 24
halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release figure 2-13 idle0 and sleep0 modes start/release 2.2.4.4 slow mode slow mode is controlled by the system control register 2 (syscr2). TMP86FH09AMG page 25
the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 to switch the main system clock to the low-frequency clock for slow2 mode. next, clear syscr2 to turn off high-frequency oscillation. note:the high-frequency clock can be continued oscillation in order to return to normal2 mode from slow mode quickly. always turn off oscillation of high-frequency clock when switching from slow mode to stop mode. when the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before per- forming the above operations. the timer/counter (tc4,tc3) can conveniently be used to confirm that low-frequency clock oscillation has stabilized. example 1 :switching from normal2 mode to slow1 mode. set (syscr2). 5 ; syscr2 1 ; (switches the main system clock to the low-frequency clock for slow2) clr (syscr2). 7 ; syscr2 0 ; (turns off high-frequency oscillation) example 2 :switching to the slow1 mode after low-frequency clock has stabilized. set (syscr2). 6 ; syscr2 1 ld (tc3cr), 43h ; sets mode for tc4, 3 (16-bit mode, fs for source) ld (tc4cr), 05h ; sets warming-up counter mode ldw (ttreg3), 8000h ; sets warm-up time (depend on oscillator accompanied) di ; imf 0 set (eirh). 3 ; enables inttc4 ei ; imf 1 set (tc4cr). 3 ; starts tc4, 3 : pinttc4: clr (tc4cr). 3 ; stops tc4, 3 set (syscr2). 5 ; syscr2 1 ; (switches the main system clock to the low-frequency clock) clr (syscr2). 7 ; syscr2 0 ; (turns off high-frequency oscillation) reti : vinttc4: dw pinttc4 ; inttc4 vector table TMP86FH09AMG 2. operational description 2.2 system clock controller page 26
(2) switching from slow1 mode to normal2 mode first, set syscr2 to turn on the high-frequency oscillation. when time for stabilization (warm up) has been taken by the timer/counter (tc4,tc3), clear syscr2 to switch the main system clock to the high-frequency clock. slow mode can also be released by inputting low level on the reset pin. after releasing re- set, the operation mode is started from normal1 mode. note:after syscr2 is cleared to 0, instructions are executed continuously by the low-fre- quency clock during synchronization period for high-frequency and low-frequency clocks. high-frequency clock low-frequency clock main system clock sysck example :switching from the slow1 mode to the normal2 mode (fc = 16 mhz, warm-up time is 4.0 ms). set (syscr2). 7 ; syscr2 1 (starts high-frequency oscillation) ld (tc3cr), 63h ; sets mode for tc4, 3 (16-bit mode, fc for source) ld (tc4cr), 05h ; sets warming-up counter mode ld ( ttreg4), 0f8h ; sets warm-up time di ; imf 0 set (eirh). 3 ; enables inttc4 ei ; imf 1 set (tc4cr). 3 ; starts tc4, 3 : pinttc4: clr (tc4cr). 3 ; stops tc4, 3 clr (syscr2). 5 ; syscr2 0 ; (switches the main system clock to the high-frequency clock) reti : vinttc4: dw pinttc4 ; inttc4 vector table TMP86FH09AMG page 27
set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode figure 2-14 switching between the normal2 and slow modes TMP86FH09AMG 2. operational description 2.2 system clock controller page 28
2.3 reset circuit the TMP86FH09AMG has four types of reset generation procedures: an external reset input, an address trap re- set, a watchdog timer reset and a system clock reset. of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. when the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 mhz) when pow- er is turned on. table 2-3 shows on-chip hardware initialization by reset action. table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at l level for at least 3 machine cycles (12/fc [s]) with the power supply volt- age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. when the reset pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses fffeh to ffffh. TMP86FH09AMG page 29
internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset figure 2-15 reset circuit 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruc- tion from the on-chip ram (when wdtcr1 is set to 1), dbr or sfr area, address trap reset will be generated. the reset time is maximum 24/fc[s] (1.5s at 16.0 mhz). note:the operating mode under address trapped is alternative of reset or interrupt. the address trap area is alternative. instruction at address r 16/fc [s] maximum 24/fc [s] instruction execution internal reset jp a reset release address trap is occurred 4/fc to 12/fc [s] note 1: address a is on-chip ram (wdtcr1 = 1) space, dbr or sfr area. note 2: during reset release, reset vector r is read out, and an instruction at address r is fetched and decoded. figure 2-16 address trap reset 2.3.3 watchdog timer reset refer to section watchdog timer. 2.3.4 system clock reset if the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the cpu. (the oscillation is continued without stopping.) - in case of clearing syscr2 and syscr2 simultaneously to 0. - in case of clearing syscr2 to 0, when the syscr2 is 0. - in case of clearing syscr2 to 0, when the syscr2 is 1. the reset time is maximum 24/fc (1.5 s at 16.0 mhz). TMP86FH09AMG 2. operational description 2.3 reset circuit page 30
3. interrupt control circuit the TMP86FH09AMG has a total of 17 interrupt sources excluding reset, of which 1 source levels are multi- plexed. interrupts can be nested with priorities. four of the internal interrupt sources are non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il), which hold interrupt requests, and independent vec- tors. the interrupt latch is set to 1 by the generation of its interrupt request which requests the cpu to accept its interrupts. interrupts are enabled or disabled by software using the interrupt master enable flag (imf) and inter- rupt enable flag (ef). if more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. interrupt factors enable condition interrupt latch vector ad- dress priority internal/external (reset) non-maskable - fffe 1 internal intswi (software interrupt) non-maskable - fffc 2 internal intundef (executed the undefined instruction interrupt) non-maskable - fffc 2 internal intatrap (address trap interrupt) non-maskable il2 fffa 2 internal intwdt (watchdog timer interrupt) non-maskable il3 fff8 2 external int0 imf? ef4 = 1, int0en = 1 il4 fff6 5 external int1 imf? ef5 = 1 il5 fff4 6 internal inttbt imf? ef6 = 1 il6 fff2 7 internal inttc1 imf? ef7 = 1 il7 fff0 8 internal intrxd imf? ef8 = 1 il8 ffee 9 internal inttxd imf? ef9 = 1 il9 ffec 10 internal inttc3 imf? ef10 = 1 il10 ffea 11 internal inttc4 imf? ef11 = 1, il11er = 0 il11 ffe8 12 external int3 imf? ef11 = 1, il11er = 1 internal intadc imf? ef12 = 1 il12 ffe6 13 internal intsei imf? ef13 = 1 il13 ffe4 14 external int4 imf? ef14 = 1 il14 ffe2 15 external int5 imf? ef15 = 1 il15 ffe0 16 note 1: the intsel register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 in- terrupt source selector (intsel)). note 2: to use the address trap interrupt (intatrap), clear wdtcr1 to 0 (it is set for the reset request after re- set is cancelled). for details, see address trap. note 3: to use the watchdog timer interrupt (intwdt), clear wdtcr1 to "0" (it is set for the "reset request" af- ter reset is released). for details, see "watchdog timer". 3.1 interrupt latches (il15 to il2) an interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is generated, the latch is set to 1, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting in- terrupt. all interrupt latches are initialized to 0 during reset. the interrupt latches are located on address 003ch and 003dh in sfr area. each latch can be cleared to "0" in- dividually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clearing the inter- rupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify-write instruc- tions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. interrupt latches are not set to 1 by an instruction. since interrupt latches can be read, the status for interrupt requests can be monitored by software. TMP86FH09AMG page 31
note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normal- ly on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". example 1 :clears interrupt latches di ; imf 0 ldw (ill), 1110100000111111b ; il12, il10 to il6 0 ei ; imf 1 example 2 :reads interrupt latches ld wa, (ill) ; w ilh, a ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset 3.2 interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the non-maska- ble interrupts (software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). non-maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt master enable flag (imf) and the individual interrupt enable flags (ef). these reg- isters are located on address 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt master enable flag (imf) the interrupt enable register (imf) enables and disables the acceptance of the whole maskable interrupt. while imf = 0, all maskable interrupts are not accepted regardless of the status on each individual inter- rupt enable flag (ef). by setting imf to 1, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to 0 after the latest status on imf is stacked. thus the maska- ble interrupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrupt acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruc- tion. the imf is normally set and cleared by [ei] and [di] instruction respectively. during reset, the imf is in- itialized to 0. 3.2.2 individual interrupt enable flags (ef15 to ef4) each of these flags enables and disables the acceptance of its maskable interrupt. setting the correspond- ing bit of an individual interrupt enable flag to 1 enables acceptance of its interrupt, and setting the bit to 0 disables acceptance. during reset, all the individual interrupt enable flags (ef15 to ef4) are initialized to 0 and all maskable interrupts are not accepted until they are set to 1. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required af- ter operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not exe- cute normally on interrupt service routine. however, if using multiple interrupt on interrupt service rou- tine, manipulating ef or il should be executed before setting imf="1". TMP86FH09AMG 3. interrupt control circuit 3.2 interrupt enable register (eir) page 32
example 1 :enables interrupts individually and sets imf di ; imf 0 ldw (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 1 : ; note: imf should not be set. : ei ; imf 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei(); interrupt latches (initial value: 00000000 000000**) ilh,ill (003dh, 003ch) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 ilh (003dh) ill (003ch) il15 to il2 interrupt latches at rd at wr r/w 0: no interrupt request 1: interrupt request 0: clears the interrupt request 1: (interrupt latch is not set.) note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on in- terrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". note 3: do not clear il with read-modify-write instructions such as bit operations. interrupt enable registers (initial value: 00000000 0000***0) eirh,eirl (003bh, 003ah) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eirh (003bh) eirl (003ah) ef15 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts note 1: *: dont care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to 1 at the same time. note 3: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on in- terrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". TMP86FH09AMG page 33
3.3 interrupt source selector (intsel) each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the intsel register. the interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the intsel register. therefore, the intsel reg- ister must be set appropriately before interrupt requests are generated. the following interrupt sources share their interrupt source level; the source is selected on the register intsel. 1. inttc4 and int3 share the interrupt source level whose priority is 12. interrupt source selector intsel (003eh) 7 6 5 4 3 2 1 0 - - - il11er - - - - (initial value: ***0 ****) il11er selects inttc4 or int3 0: inttc4 1: int3 r/w note:always set "0" to bit 5 of intsel register. 3.4 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to 0 by resetting or an instruction. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) af- ter the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt re- turn instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the tim- ing chart of interrupt acceptance processing. 3.4.1 interrupt acceptance processing is packaged as follows. a. the interrupt master enable flag (imf) is cleared to 0 in order to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to 0. c. the contents of the program counter (pc) and the program status word, including the interrupt mas- ter enable flag (imf), are saved (pushed) on the stack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (sp) is decremented by 3. d. the entry address (interrupt vector) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the interrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. TMP86FH09AMG 3. interrupt control circuit 3.3 interrupt source selector (intsel) page 34
a b a c+1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2 n ? 1 n ? 1 n a+2 a+1 c+2 b + 3 b+2 b+1 a+1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return interrupt instruction example: correspondence between vector table address for inttbt and the entry address of the interrupt service program d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff2h fff3h a maskable interrupt is not accepted until the imf is set to 1 even if the maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to 1 in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serv- iced, before setting imf to 1. as for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 saving/restoring general-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw, in- cludes imf) are automatically saved on the stack, but the accumulator and others are not. these registers are saved by software if necessary. when multiple interrupt services are nested, it is also necessary to avoid us- ing the same data memory area for saving registers. the following methods are used to save/restore the general- purpose registers. 3.4.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the push/pop instructions. TMP86FH09AMG page 35
example :save/store register using push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5 3.4.2.2 using data transfer instructions to save only a specific register without nested interrupts, data transfer instructions are available. example :save/store register using data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task figure 3-2 saving/restoring general-purpose registers under interrupt processing 3.4.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. TMP86FH09AMG 3. interrupt control circuit 3.4 interrupt sequence page 36
[reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. as for address trap interrupt (intatrap), it is required to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again. when interrupt acceptance processing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return example 2 :restarting without returning interrupt (in this case, psw (includes imf) before interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to 1 or clear it to 0 jp restart address ; jump into restarting address interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediately after the interrupt return instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return in- terrupt instruction [retn] is not utilized during interrupt service program under intatrap (such as exam- ple 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt serv- ice task is performed but not the main task. 3.5 software interrupt (intsw) executing the swi instruction generates a software interrupt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.5.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent mem- ory address during single chip mode. code ffh is the swi instruction, so a software interrupt is generated and an address error is detected. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. TMP86FH09AMG page 37
3.5.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting ad- dress. 3.6 undefined instruction interrupt (intundef) taking code which is not defined as authorized instruction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a code and tries to execute it. intundef is accepted even if non-maskable in- terrupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is reques- ted. note:the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software inter- rupt (swi) does. 3.7 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructions (address trapped area) causes reset output or ad- dress trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contempo- rary process is broken and intatrap interrupt process starts, soon after it is requested. note:the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). 3.8 external interrupts the TMP86FH09AMG has 5 external interrupt inputs. these inputs are equipped with digital noise reject cir- cuits (pulse inputs of less than a certain time are eliminated as noise). edge selection is also possible with int1 to int4. the int0/p10 pin can be configured as either an external in- terrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0/p10 pin function selection are performed by the external interrupt control register (eintcr). TMP86FH09AMG 3. interrupt control circuit 3.6 undefined instruction interrupt (intundef) page 38
source pin enable conditions release edge (level) digital noise reject int0 int0 imf ef4 int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are consid- ered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are elimina- ted as noise. pulses of 3.5/fs [s] or more are considered to be signals. int1 int1 imf ef5 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimina- ted as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int3 int3 imf ef11 = 1 and il11er=1 falling edge, rising edge, falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are consid- ered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int4 int4 imf ef14 = 1 falling edge, rising edge, falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are consid- ered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int5 int5 imf ef15 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are consid- ered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are elimina- ted as noise. pulses of 3.5/fs [s] or more are considered to be signals. note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il4 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an output and a change occurs in data or input/output status, an in- terrupt request signal is generated in a pseudo manner. in this case, it is necessary to perform appropriate process- ing such as disabling the interrupt enable flag. external interrupt control register eintcr 7 6 5 4 3 2 1 0 (0037h) int1nc int0en int3es int4es int1es (initial value: 0000 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p10/ int0 pin configuration 0: p10 input/output port 1: int0 pin (port p10 should be set to an input mode) r/w int4 es int4 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: "h" level r/w int3 es int3 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: "h" level r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w note 1: fc: high-frequency clock [hz], *: dont care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operate normally. it is recommended that external interrupts are disabled using the interrupt enable register (eir). TMP86FH09AMG page 39
note 3: the maximum time from modifying int1nc until a noise reject time is changed is 2 6 /fc. note 4: in case reset pin is released while the state of int3 pin keeps "h" level, the external interrupt 3 request is not gen- erated even if the int3 edge select is specified as "h" level. the rising edge is needed after reset pin is released. note 5: in case reset pin is released while the state of int4 pin keeps "h" level, the external interrupt 4 request is not gen- erated even if the int4 edge select is specified as "h" level. the rising edge is needed after reset pin is released. TMP86FH09AMG 3. interrupt control circuit 3.8 external interrupts page 40
4. special function register (sfr) the TMP86FH09AMG adopts the memory mapped i/o system, and all peripheral control and data transfers are performed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special function register (sfr) and data buffer register (dbr) for TMP86FH09AMG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h reserved 0005h reserved 0006h reserved 0007h reserved 0008h reserved 0009h p1cr 000ah p3cr 000bh p0outcr 000ch p0prd - 000dh p2prd - 000eh adccr1 000fh adccr2 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h tc1cr 0015h reserved 0016h reserved 0017h reserved 0018h reserved 0019h reserved 001ah tc3cr 001bh tc4cr 001ch ttreg3 001dh ttreg4 001eh pwreg3 001fh pwreg4 0020h adcdr2 - 0021h adcdr1 - 0022h reserved 0023h reserved 0024h reserved 0025h uartsr uartcr1 TMP86FH09AMG page 41
address read write 0026h - uartcr2 0027h rdbuf tdbuf 0028h sesr - 0029h sedr 002ah secr 002bh reserved 002ch reserved 002dh reserved 002eh reserved 002fh reserved 0030h reserved 0031h - stopcr 0032h reserved 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh intsel 003fh psw note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP86FH09AMG 4. special function register (sfr) 4.1 sfr page 42
4.2 dbr address read write 0f80h reserved : : : : 0f9fh reserved address read write 0fa0h reserved : : : : 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved address read write 0fe0h reserved 0fe1h reserved 0fe2h reserved 0fe3h reserved 0fe4h reserved 0fe5h reserved 0fe6h reserved 0fe7h reserved 0fe8h reserved 0fe9h - flsstb 0feah spcr 0febh reserved 0fech reserved 0fedh reserved 0feeh reserved 0fefh reserved 0ff0h reserved 0ff1h reserved 0ff2h reserved 0ff3h reserved 0ff4h reserved 0ff5h reserved 0ff6h reserved 0ff7h reserved 0ff8h reserved 0ff9h reserved 0ffah reserved 0ffbh reserved 0ffch reserved 0ffdh reserved 0ffeh reserved TMP86FH09AMG page 43
address read write 0fffh flscr note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP86FH09AMG 4. special function register (sfr) 4.2 dbr page 44
5. i/o ports the TMP86FH09AMG have 4 parallel input/output ports as follows. primary function secondary functions port p0 8-bit i/o port external interrupt input, timer/counter input/output, serial interface input/out- put, serial prom mode control input/output. port p1 7-bit i/o port external interrupt input and divider output port p2 3-bit i/o port external interrupt input and stop mode release signal input port p3 8-bit i/o port analog input, stop mode release signal input and timer/counter input/output each output port contains a latch, which holds the output data. all input ports do not have latches, so the exter- nal input data should be externally held until the input data is read from outside or reading should be performed sev- eral timer before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. output data changes in the s2 state of the write cycle during execution of the instruction which writes to an i/ o port. note:the positions of the read and write cycles may vary, depending on the instruction. figure 5-1 input/output timing (example) TMP86FH09AMG page 45  
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5.1 p0 (p07 to p00) port (high current) the p0 port is an 8-bit input/output port shared with external interrupt input, sei serial interface input/output, and uart and 16-bit timer counter input/output. when using this port as an input port or for external interrupt in- put, sei serial interface input/output, or uart input/output, set the output latch to 1. when using this port as an out- put port, the output latch data (p0dr) is output to the p0 port. when reset, the output latch (p0dr) and the push-pull control register (p0outcr) are initialized to 1 and 0, re- spectively. the p0 port allows its output circuit to be selected between n-channel open-drain output or push-pull out- put by the p0outcr register. when using this port as an input port, set the p0outcr register's corresponding bit to 0 after setting the p0dr to 1. the p0 port has independent data input registers. to inspect the output latch status, read the p0dr reg- ister. to inspect the pin status, read the p0prd register. in the serial prom mode, p02 pin used as a boot/rxd0 pin, p03 pin used as a txd0 pin. for details, see "se- rial prom mode setting". in the mcu mode, p01 pin used as a rxd pin, p00 pin used as a txd pin. figure 5-2 p0 port p0dr (0000h) r/w 7 6 5 4 3 2 1 0 p07 tc1 int4 p06 int3 ppg p05 ss p04 miso p03 mos (txd0) p02 sclk (boot/ rxd0) p01 rxd p00 txd (initial value: 1111 1111) p0prd (000ch) read only 7 6 5 4 3 2 1 0 p07 p06 p05 p04 p03 p02 p01 p00 p0outcr (000bh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p0outcr controls p0 port input/output (specified bitwise) 0: nch open-drain output 1: push-pull output r/w TMP86FH09AMG 5. i/o ports 5.1 p0 (p07 to p00) port (high current) page 46    
  

  
        
  
         
 
 
5.2 p1 (p16 to p10) port the p1 port is a 7-bit input/output port that can be specified for input or output bitwise. the p1 port input/out- put control register (p1cr) is used to specify this port for input or output. when reset, the p1cr register is initial- ized to 0, with the p1 port set for input mode. the p1 port output latch is initialized to 0. the p1 port is shared with external interrupt input and divider output. when using the p1 port as function pin, set its input pins for input mode. for the output pins, first set their output latches to 1 before setting the pins for out- put mode. note that the p11 pin is an external interrupt input. (when used as an output port, its interrupt latch is set at the rising or falling edge.) the p10 pin can be used as an input/output port or an external interrupt input by selecting its function with the external interrupt control register (int0en). when reset, the p10 pin is chosen to be an in- put port. figure 5-3 p1 port p1dr (0001h) r/w 7 6 5 4 3 2 1 0 p16 p15 p14 p13 p12 dvo p11 int1 p10 int0 (initial value: ***0 0000) p1cr (0009h) 7 6 5 4 3 2 1 0 (initial value: ***0 0000) p1cr controls p1 port input/output (specified bitwise) 0: input mode 1: output mode r/w TMP86FH09AMG page 47 output latch p1cri data output (p1dr) output latch p1cri input control output stop outen data input (p1dr) control input p1i note: i = 6 to 0 dq dq
5.3 p2 (p22 to p20) port the p2 port is a 3-bit input/output port shared with external interrupt input, stop canceling signal input, and low-frequency resonator connecting pin. when using this port as an input port or function pin, set the output latch to 1. the output latch is initialized to 1 when reset. when operating in dual-clock mode, connect a low-frequency resonator (32.768 khz) to the p21 (xtin) and p22 (xtout) pins. when operating in single-clock mode, the p21 and p22 pins can be used as ordinary input/output ports. we recommend using the p20 pin for external inter- rupt input or stop canceling signal input or as an input port. (when used as an output port, the interrupt latch is set by a falling edge.) the p2 port has independent data input registers. to inspect the output latch status, read the p2dr register. to in- spect the pin status, read the p2prd register. when the p2dr or p2prd read instruction is executed for the p2 port, the values read from bits 7 to 3 are indeterminate. figure 5-4 p2 port p2dr (0002h) r/w 7 6 5 4 3 2 1 0 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (000dh) read only 7 6 5 4 3 2 1 0 p22 p21 p20 note:the p20 pin is shared with the stop pin, so that when in stop mode, its output goes to a high-z state regard- less of the outen status. TMP86FH09AMG 5. i/o ports 5.3 p2 (p22 to p20) port page 48      
  

  
 
 
     
  

  
  

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5.4 p3 (p37 to p30) port the p3 port is an 8-bit input/output port that can be specified for input or output bitwise, and is shared with ana- log input, key-on wakeup input, and 8-bit timer counter input/output. the p3 port input/output control register (p3cr) and adccr1 are used to specify this port for input or output. when reset, the p3cr register and p3dr are cleared to 0, while ainds is set to 1, so that p37 to p30 function as input port. when using the p3 port as an input port, set ainds = 1 while at the same time setting the p3cr register to 0. when using the p3 port for analog input, set ainds = 0 and the pins selected with adccr1 are set for analog input no matter what values are set in the p3dr and p3cr. when using the p3 port as an output port, set the p3cr to 1 and the pin associated with that bit is set for output mode, so that p3dr (output latch data) is out- put from that pin. when an input instruction is executed for the p3 port while using the ad converter, the pins selected for ana- log input read in the p3dr value into the internal circuit and those not selected for analog input read in a 1 or 0 ac- cording to the logic level on each pin. even when an output instruction is executed, no latch data are forwarded to the pins selected for analog input. any pins of the p3 port which are not used for analog input can be used as input/output ports. during ad conver- sion, however, avoid executing output instructions on these ports, because this is necessary to maintain the accura- cy of conversion. also, during ad conversion, take care not to enter a rapidly changing signal to any port adja- cent to analog input. figure 5-5 p3 port TMP86FH09AMG page 49 output latch output latch data input (p3dr) analog input key-on wakeup data output (p3dr) stop stopnen outen ainds sain p3cri p3cri input p3i note 1: i = 7 to 2 note 2: n = 7 to 4 note 3: functions enclosed with broken lines do not apply to p32 and p33. output latch output latch data input (p3dr) data output (p3dr) control input a) equivalent circuit of p32 to p37 b) equivalent circuit of p30, p31 control output stop outen p3cri p3cri input p3i note: i = 1 to 0
p3dr (0003h) r/w 7 6 5 4 3 2 1 0 p37 ain5 stop5 p36 ain4 stop4 p35 ain3 stop3 p34 ain2 stop2 p33 ain1 p32 ain0 p31 tc4 pdo4 pwm4 ppg4 p30 tc3 pdo3 pwm3 (initial value: 0000 0000) p3cr (000ah) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p3cr controls p3 port output (speci- fied bitwise) 0: input mode 1: output mode r/w analog input mode input mode output mode p3cr 0 1 ainds 0 1 p3dr 0 * note 1: when using the port for key-on wakeup input (stop2 to 5), set the p3cr register's corresponding bits to 0. note 2: p30 and p31 are hysteresis inputs. p34 to p37 become hysteresis inputs only during key-on wakeup. note 3: input status on ports set for input mode are read in into the internal circuit. therefore, when using the ports in a mix- ture of input and output modes, the contents of the output latches for the ports that are set for input mode may be re- written by execution of bit manipulating instructions. TMP86FH09AMG 5. i/o ports 5.4 p3 (p37 to p30) port page 50
6. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 6.1 time base timer 6.1.1 configuration figure 6-1 time base timer configuration 6.1.2 control time base timer is controlled by time base timer control register (tbtcr). time base timer control register 7 6 5 4 3 2 1 0 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 - 011 fc/2 14 fs/2 6 - 100 fc/2 13 fs/2 5 - 101 fc/2 12 fs/2 4 - 110 fc/2 11 fs/2 3 - 111 fc/2 9 fs/2 - note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz], *; don't care TMP86FH09AMG page 51 fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request
note 2: the interrupt frequency (tbtck) must be selected with the time base timer disabled (tbten = "0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 ld (tbtcr) , 00001010b ; tbten 1 di ; imf 0 set (eirl) . 6 table 6-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 - 011 976.56 512 - 100 1953.13 1024 - 101 3906.25 2048 - 110 7812.5 4096 - 111 31250 16384 - 6.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divid- er output of the timing generator which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 6-2 ). figure 6-2 time base timer interrupt TMP86FH09AMG 6. time base timer (tbt) 6.1 time base timer page 52 source clock enable tbt interrupt period tbtcr inttbt
6.2 divider output ( dvo) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buz- zer drive. divider output is from dvo pin. 6.2.1 configuration figure 6-3 divider output 6.2.2 control the divider output is controlled by the time base timer control register. time base timer control register 7 6 5 4 3 2 1 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 note:selection of divider output frequency (dvock) must be made while divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequency from enabled (dvoen="1") to dis- able(dvoen="0"), do not change the setting of the divider output frequency. TMP86FH09AMG page 53 tbtcr output latch port output latch mpx dvoen tbtcr dvo pin output dvock divider output control register (a) configuration (b) timing chart data output 2 a b c d s dvo pin dq y fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 10 or fs/2 2
example :1.95 khz pulse output (fc = 16.0 mhz) setting port ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 6-2 divider output frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k TMP86FH09AMG 6. time base timer (tbt) 6.2 divider output ( dvo) page 54
7. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a system recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as reset request or inter- rupt request. upon the reset release, this signal is initialized to reset request. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic in- terrupt. note:care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 figure 7-1 watchdog timer configuration TMP86FH09AMG page 55
7.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 7.2.1 malfunction detection methods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as endless loops or the deadlock conditions occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 is set to 1 at this time, the reset request is generated and then internal hardware is in- itialized. when wdtcr1 is set to 0, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in the stop mode including the warm-up or idle/ sleep mode, and automatically restarts (continues counting) when the stop/idle/sleep mode is inactiva- ted. note:the watchdog timer consists of an internal divider and a two-stage binary counter. when the clear code 4eh is written, only the binary counter is cleared, but not the internal divider. the minimum bina- ry-counter overflow time, that depends on the timing at which the clear code (4eh) is written to the wdtcr2 register, may be 3/4 of the time set in wdtcr1. therefore, write the clear code us- ing a cycle shorter than 3/4 of the time set to wdtcr1. example :setting the watchdog timer detection time to 2 21 /fc [s], and resetting the cpu malfunction detection ld (wdtcr2), 4eh : clears the binary counters. ld (wdtcr1), 00001101b : wdtt 10, wdtout 1 ld (wdtcr2), 4eh : clears the binary counters (always clears immediately before and after changing wdtt). within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters. within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters. TMP86FH09AMG 7. watchdog timer (wdt) 7.2 watchdog timer control page 56
watchdog timer control register 1 wdtcr1 (0034h) 7 6 5 4 3 2 1 0 (atas) (atout) wdten wdtt wdtout (initial value: **11 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal1/2 mode slow1/2 mode write only dv7ck = 0 dv7ck = 1 00 2 25 /fc 2 17 /fs 2 17 /fs 01 2 23 /fc 2 15 /fs 2 15 fs 10 2 21 fc 2 13 /fs 2 13 fs 11 2 19 /fc 2 11 /fs 2 11 /fs wdtout watchdog timer output select 0: interrupt request 1: reset request write only note 1: after clearing wdtout to 0, the program cannot set it to 1. note 2: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *: dont care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a dont care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance with the procedures shown in 7.2.3 watchdog timer disable. watchdog timer control register 2 wdtcr2 (0035h) 7 6 5 4 3 2 1 0 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) d2h: enable assigning address trap area others: invalid write only note 1: the disable code is valid only when wdtcr1 = 0. note 2: *: dont care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: write the clear code 4eh using a cycle shorter than 3/4 of the time set in wdtcr1. 7.2.2 watchdog timer enable setting wdtcr1 to 1 enables the watchdog timer. since wdtcr1 is initialized to 1 during reset, the watchdog timer is enabled automatically after the reset release. TMP86FH09AMG page 57
7.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the following procedures. setting the reg- ister in other procedures causes a malfunction of the micro controller. 1. set the interrupt master flag (imf) to 0. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 to 0. 4. set wdtcr2 to the disable code (b1h). note:while the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. example :disabling the watchdog timer di : imf 0 ld (wdtcr2), 04eh : clears the binary counter ldw (wdtcr1), 0b101h : wdten 0, wdtcr2 disable code table 7-1 watchdog timer detection time (example: fc = 16.0 mhz, fs = 32.768 khz) wdtt watchdog timer detection time[s] normal1/2 mode slow mode dv7ck = 0 dv7ck = 1 00 2.097 4 4 01 524.288 m 1 1 10 131.072 m 250 m 250 m 11 32.768 m 62.5 m 62.5 m 7.2.4 watchdog timer interrupt (intwdt) when wdtcr1 is cleared to 0, a watchdog timer interrupt request (intwdt) is gener- ated by the binary-counter overflow. a watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt master flag (imf). when a watchdog timer interrupt is generated while the other interrupt including a watchdog timer inter- rupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous inter- rupt is held pending. therefore, if watchdog timer interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate a watchdog timer interrupt, set the stack pointer before setting wdtcr1. example :setting watchdog timer interrupt ld sp, 023fh : sets the stack pointer ld (wdtcr1), 00001000b : wdtout 0 TMP86FH09AMG 7. watchdog timer (wdt) 7.2 watchdog timer control page 58
7.2.5 watchdog timer reset when a binary-counter overflow occurs while wdtcr1 is set to 1, a watchdog timer reset request is generated. when a watchdog timer reset request is generated, the internal hardware is reset. the re- set time is maximum 24/fc [s] (1.5 s @ fc = 16.0 mhz). note:when a watchdog timer reset is generated in the slow1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. however, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be consid- ered as an approximate value because it has slight errors. clock binary counter overflow intwdt interrupt request (wdtcr1= "0") 2 17 /fc 2 19 /fc [s] (wdtt=11) write 4e h to wdtcr2 1 2 30 1 2 3 0 internal reset (wdtcr1= "1") a reset occurs figure 7-2 watchdog timer interrupt TMP86FH09AMG page 59
7.3 address trap the watchdog timer control register 1 and 2 share the addresses with the control registers to generate ad- dress traps. watchdog timer control register 1 wdtcr1 (0034h) 7 6 5 4 3 2 1 0 atas atout (wdten) (wdtt) (wdtout) (initial value: **11 1001) atas select address trap generation in the internal ram area 0: generate no address trap 1: generate address traps (after setting atas to 1, writing the control code d2h to wdtcr2 is required) write only atout select operation at address trap 0: interrupt request 1: reset request watchdog timer control register 2 wdtcr2 (0035h) 7 6 5 4 3 2 1 0 (initial value: **** ****) wdtcr2 write watchdog timer control code and address trap area control code d2h: enable address trap area selection (atrap control code) 4eh: clear the watchdog timer binary counter (wdt clear code) b1h: disable the watchdog timer (wdt disable code) others: invalid write only 7.3.1 selection of address trap in internal ram (atas) wdtcr1 specifies whether or not to generate address traps in the internal ram area. to exe- cute an instruction in the internal ram area, clear wdtcr1 to 0. to enable the wdtcr1 setting, set wdtcr1 and then write d2h to wdtcr2. executing an instruction in the sfr or dbr area generates an address trap unconditionally regardless of the setting in wdtcr1. 7.3.2 selection of operation at address trap (atout) when an address trap is generated, either the interrupt request or the reset request can be selected by wdtcr1. 7.3.3 address trap interrupt (intatrap) while wdtcr1 is 0, if the cpu should start looping for some cause such as noise and an at- tempt be made to fetch an instruction from the on-chip ram (while wdtcr1 is 1), dbr or the sfr area, address trap interrupt (intatrap) will be generated. an address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas- ter flag (imf). when an address trap interrupt is generated while the other interrupt including an address trap interrupt is al- ready accepted, the new address trap is processed immediately and the previous interrupt is held pending. there- fore, if address trap interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate address trap interrupts, set the stack pointer beforehand. TMP86FH09AMG 7. watchdog timer (wdt) 7.3 address trap page 60
7.3.4 address trap reset while wdtcr1 is 1, if the cpu should start looping for some cause such as noise and an at- tempt be made to fetch an instruction from the on-chip ram (while wdtcr1 is 1), dbr or the sfr area, address trap reset will be generated. when an address trap reset request is generated, the internal hardware is reset. the reset time is maximum 24/fc [s] (1.5 s @ fc = 16.0 mhz). note:when an address trap reset is generated in the slow1 mode, the reset time is maximum 24/fc (high- frequency clock) since the high-frequency clock oscillator is restarted. however, when crystals have in- accuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. TMP86FH09AMG page 61
TMP86FH09AMG 7. watchdog timer (wdt) 7.3 address trap page 62
8. 16-bit timer/counter 1 (tc1) 8.1 configuration :::? pin tc1:w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3 figure 8-1 timercounter 1 (tc1) TMP86FH09AMG page 63
8.2 timer/counter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer regis- ters (tc1dra and tc1drb). timer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write enabled only in the ppg output mode) timercounter 1 control register tc1cr (0014h) 7 6 5 4 3 2 1 0 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0 : auto-capture disable 1 : auto-capture enable r/w mcap1 pulse width measure- ment mode control 0 :double edge capture 1 : single edge capture mett1 external trigger timer mode control 0 : trigger start 1 : trigger start and stop mppg1 ppg output control 0 : continuous pulse generation 1 : one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear o o o o o o 01: command start o - - - - o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) - o o o o o 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) - o o o o o tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 - 10 fc/2 3 fc/2 3 dv1 - 11 external clock (tc1 pin input) tc1m tc1 operating mode se- lect 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (tc1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruc- tion). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.2 timer/counter control page 64
note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc1cr during tc1s=00. set the tim- er f/f1 control until the first timer start after setting the ppg mode. note 4: auto-capture can be used only in the timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tff1 to 0 in the mode except ppg output mode. note 7: set tc1drb after setting tc1m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1s) is cleared to 00 automatically, and the timer stops. after the stop mode is exited, set the tc1s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock be- fore reading tc1drb for the first time. TMP86FH09AMG page 65
8.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-coun- ter and the timer register 1a (tc1dra) value is detected, an inttc1 interrupt is generated and the up-coun- ter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr to 1 captures the up-counter value into the timer register 1b (tc1drb) with the auto-capture function. use the auto-cap- ture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execu- tion of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. table 8-1 internal source clock for timercounter 1 (example: fc = 16 mhz, fs = 32.768 khz) tc1ck normal1/2, idle1/2 mode slow, sleep mode dv7ck = 0 dv7ck = 1 resolution [s] maximum time setting [s] resolution [s] maximum time setting [s] resolution [s] maximum time setting [s] 00 128 8.39 244.14 16.0 244.14 16.0 01 8.0 0.524 8.0 0.524 - - 10 0.5 32.77 m 0.5 32.77 m - - example 1 :setting the timer mode with source clock fc/2 11 [hz] and generating an interrupt 1 second later (fc = 16 mhz, tbtcr = 0) ldw (tc1dra), 1e84h ; sets the timer register (1 s 2 11 /fc = 1e84h) di ; imf= 0 set (eirl). 7 ; enables inttc1 ei ; imf= 1 ld (tc1cr), 00000000b ; selects the source clock and mode ld (tc1cr), 00010000b ; starts tc1 example 2 :auto-capture ld (tc1cr), 01010000b ; acap1 1 : : ld wa, (tc1drb) ; reads the capture value note:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 66
match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 32 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1 figure 8-2 timer mode timing chart TMP86FH09AMG page 67
8.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the ris- ing or falling edge is defined in tc1cr. ? when tc1cr is set to 1 (trigger start and stop) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. if the edge opposite to trigger edge is detected before detecting a match between the up-counter and the tc1dra, the up-counter is cleared and halted without generating an interrupt request. there- fore, this mode can be used to detect exceeding the specified pulse by interrupt. after being halted, the up-counter restarts counting when the trigger edge is detected. ? when tc1cr is set to 0 (trigger start) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. the edge opposite to the trigger edge has no effect in count up. the trigger edge for the next count- ing is ignored if detecting it before detecting a match between the up-counter and the tc1dra. since the tc1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. a pulse width of 12/fc [s] or more is required to ensure edge detection. the rejection circuit is turned off in the slow1/2 or sleep1/2 mode, but a pulse width of one machine cycle or more is required. example 1 :generating an interrupt 1 ms after the rising edge of the input pulse to the tc1 pin (fc = 16 mhz) ldw (tc1dra), 007dh ; 1ms 2 7 /fc = 7dh di ; imf= 0 set (eirl). 7 ; enables inttc1 interrupt ei ; imf= 1 ld (tc1cr), 00000100b ; selects the source clock and mode ld (tc1cr), 00100100b ; starts tc1 external trigger, mett1= 0 example 2 :generating an interrupt when the low-level pulse with 4 ms or more width is input to the tc1 pin (fc = 16 mhz) ldw (tc1dra), 01f4h ; 4 ms 2 7 /fc = 1f4h di ; imf= 0 set (eirl). 7 ; enables inttc1 interrupt ei ; imf= 1 ld (tc1cr), 00000100b ; selects the source clock and mode ld (tc1cr), 01110100b ; starts tc1 external trigger, mett1= 1 TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 68
inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear figure 8-3 external trigger timer mode timing chart TMP86FH09AMG page 69
8.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is selected as the count up edge in tc1cr. when a match between the up-counter and the tc1dra value is detected, an inttc1 interrupt is gener- ated and the up-counter is cleared. after being cleared, the up-counter restarts counting at each edge of the in- put pulse to the tc1 pin. since a match between the up-counter and the value set to tc1dra is detected at the edge opposite to the selected edge, an inttc1 interrupt request is generated after a match of the value at the edge opposite to the selected edge. two or more machine cycles are required for the low-or high-level pulse input to the tc1 pin. setting tc1cr to 1 captures the up-counter value into tc1drb with the auto capture func- tion. use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the capture value in a capture ena- bled condition. since the up-counter value is captured into tc1drb by the source clock of up-counter after set- ting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. at the rising edge (tc1s = 10) inttc1 interrput request tc1 pin input up-counter tc1dra ? 2 1 0 n timer start 2 1 0 n match detect counter clear n ? 1 figure 8-4 event counter mode timing chart table 8-2 input pulse width to tc1 pin minimum pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode high-going 2 3 /fc 2 3 /fs low-going 2 3 /fc 2 3 /fs TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 70
8.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded prod- uct of the input pulse to the tc1 pin (window pulse) and the internal source clock. either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra value is detected, an inttc1 interrupt is gener- ated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock program- med with tc1cr. match detect tc1dra inttc1 interrput request interrput request internal clock counter tc1dra tc1 pin input internal clock counter tc1 pin input inttc1 (a) positive logic (tc1s = 10) (b) negative logic (tc1s = 11) ? ? match detect 1 0 7 47 5 46 31 21 0 7 5 3 6 2 0 2 3 counter clear timer start 8 90 1 9 timer start counter clear count start count stop count start count start count stop count start figure 8-5 window mode timing chart TMP86FH09AMG page 71
8.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr. either the single- or double-edge capture is selected as the trigger edge in tc1cr. ? when tc1cr is set to 1 (single-edge capture) either high- or low-level input pulse width can be measured. to measure the high-level input pulse width, set the rising edge to tc1cr. to measure the low-level input pulse width, set the falling edge to tc1cr. when detecting the edge opposite to the trigger edge used to start counting after the timer starts, the up-counter captures the up-counter value into tc1drb and generates an inttc1 interrupt re- quest. the up-counter is cleared at this time, and then restarts counting when detecting the trigger edge used to start counting. ? when tc1cr is set to 0 (double-edge capture) the cycle starting with either the high- or low-going input pulse can be measured. to measure the cycle starting with the high-going pulse, set the rising edge to tc1cr. to measure the cycle starting with the low-going pulse, set the falling edge to tc1cr. when detecting the edge opposite to the trigger edge used to start counting after the timer starts, the up-counter captures the up-counter value into tc1drb and generates an inttc1 interrupt re- quest. the up-counter continues counting up, and captures the up-counter value into tc1drb and generates an inttc1 interrupt request when detecting the trigger edge used to start counting. the up-counter is cleared at this time, and then continues counting. note 1: the captured value must be read from tc1drb until the next trigger edge is detected. if not read, the cap- tured value becomes a dont care. it is recommended to use a 16-bit access instruction to read the cap- tured value from tc1drb. note 2: for the single-edge capture, the counter after capturing the value stops at 1 until detecting the next edge. therefore, the second captured value is 1 larger than the captured value immediately after count- ing starts. note 3: the first captured value after the timer starts may be read incorrectively, therefore, ignore the first period captured values. TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 72
example :duty measurement (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 service switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf= 0 set (eirl). 7 ; enables inttc1 ei ; imf= 1 ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 : pinttc1: cpl (inttc1sw). 0 ; inttc1 interrupt, inverts and tests inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (high-level pulse width) ld w,(tc1drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc1: ld a, (tc1drbl) ; reads tc1drb (cycle) ld w,(tc1drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc1: dw pinttc1 ; inttc1 interrupt vector width hpulse tc1 pin inttc1 interrupt request inttc1sw TMP86FH09AMG page 73
tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 321 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 321 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture figure 8-6 pulse width measurement mode TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 74
8.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. to start the timer, tc1cr specifies either the edge of the input pulse to the tc1 pin or the command start. tc1cr specifies whether a duty pulse is produced continuous- ly or not (one-shot pulse). ? when tc1cr is set to 0 (continuous pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter con- tinues counting. when a match between the up-counter and the tc1dra value is detected, the lev- el of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter is cleared at this time, and then continues counting and pulse generation. when tc1s is cleared to 00 during ppg output, the ppg pin retains the level immediately be- fore the counter stops. ? when tc1cr is set to 1 (one-shot pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter con- tinues counting. when a match between the up-counter and the tc1dra value is detected, the lev- el of the ppg pin is inverted and an inttc1 interrupt request is generated. tc1cr is cleared to 00 automatically at this time, and the timer stops. the pulse generated by ppg retains the same level as that when the timer stops. since the output level of the ppg pin can be set with tc1cr when the timer starts, a positive or neg- ative pulse can be generated. since the inverted level of the timer f/f1 output level is output to the ppg pin, specify tc1cr to 0 to set the high level to the ppg pin, and 1 to set the low level to the ppg pin. upon reset, the timer f/f1 is initialized to 0. note 1: to change tc1dra or tc1drb during a run of the timer, set a value sufficiently larger than the count val- ue of the counter. setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. note 2: do not change tc1cr during a run of the timer. tc1cr can be set correctly only at initi- alization (after reset). when the timer stops during ppg, tc1cr can not be set correctly from this point onward if the ppg output has the level which is inverted of the level when the timer starts. (set- ting tc1cr specifies the timer f/f1 to the level inverted of the programmed value.) therefore, the timer f/f1 needs to be initialized to ensure an arbitrary level of the ppg output. to initialize the tim- er f/f1, change tc1cr to the timer mode (it is not required to start the timer mode), and then set the ppg mode. set tc1cr at this time. note 3: in the ppg mode, the following relationship must be satisfied. tc1dra > tc1drb note 4: set tc1drb after changing the mode of tc1m to the ppg mode. example :generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc s = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer TMP86FH09AMG page 75
example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc s = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer : : ld (tc1cr), 10000111b ; stops the timer ld (tc1cr), 10000100b ; sets the timer mode ld (tc1cr), 00000111b ; sets the ppg mode, tff1 = 0 ld (tc1cr), 00010111b ; starts the timer q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr write to tc1cr internal reset match to tc1drb match to tc1dra tc1cr clear timer f/f1 inttc1 interrupt request figure 8-7 ppg output TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 76
inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m0 1 2 n m0 1 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output figure 8-8 ppg mode timing chart TMP86FH09AMG page 77
TMP86FH09AMG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 78
9. 8-bit timercounter (tc3, tc4) 9.1 configuration figure 9-1 8-bit timercounter 3, 4 TMP86FH09AMG page 79 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4 /pwm 4 / ppg 4 pin pdo 3 /pwm 3 / pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3
9.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer regis- ters (ttreg3, pwreg3). timercounter 3 timer register ttreg3 (001ch) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg3 (001eh) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 3 control register tc3cr (001ah) 7 6 5 4 3 2 1 0 tff3 tc3ck tc3s tc3m (initial value: 0000 0000) tff3 time f/f3 control (note 2,3) 0: 1: clear set r/w tc3ck operating clock selection [hz] (note 2,3,6) normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 - 010 fc/2 5 fc/2 5 - 011 fc/2 3 fc/2 3 - 100 fs fs fs 101 fc/2 fc/2 - 110 fc (note 8) fc (note 8) fc (note 8) 111 tc3 pin input tc3s tc3 start control (note 3) 0: 1: operation stop and counter clear operation start r/w tc3m tc3m operating mode select (note 2,3,7) 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode 16-bit mode (note 4,5) (each mode is selectable with tc4m.) reserved r/w note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer op- eration (tc3s= 0 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set the operating mode by programming tc4cr, where tc3m must be fixed to 011. note 5: to use the timercounter in the 16-bit mode, select the source clock by programming tc3ck. set the timer start con- trol and timer f/f control by programming tc4cr and tc4cr, respectively. note 6: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see ta- ble 9-1 and table 9-2. note 7: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see ta- ble 9-3. TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.2 timercounter control page 80
note 8: the clock "fc" can be selected as the source clock only in 8/16 bit pwm mode and in warming-up counter mode in slow or sleep mode. TMP86FH09AMG page 81
the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer regis- ters (ttreg4 and pwreg4). timercounter 4 timer register ttreg4 (001dh) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg4 (001fh) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 4 control register tc4cr (001bh) 7 6 5 4 3 2 1 0 tff4 tc4ck tc4s tc4m (initial value: 0000 0000) tff4 timer f/f4 control (note 2,3) 0: 1: clear set r/w tc4ck operating clock selection [hz] (note 2,3,7) normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 - 010 fc/2 5 fc/2 5 - 011 fc/2 3 fc/2 3 - 100 fs fs fs 101 fc/2 fc/2 - 110 fc (note 9) fc (note 9) - 111 tc4 pin input tc4s tc4 start control (note 3) 0: 1: operation stop and counter clear operation start r/w tc4m tc4m operating mode select (note 2,3,8) 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode reserved 16-bit timer/event counter mode warm-up counter mode 16-bit pulse width modulation (pwm) output mode 16-bit ppg mode r/w note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the source clock becomes the tc3 overflow signal regardless of the tc4ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr must be set to 011. note 6: to the timercounter in the 16-bit mode, select the source clock by programming tc3cr. set the timer start control and timer f/f control by programming tc4s and tff4, respectively. TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.2 timercounter control page 82
note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see ta- ble 9-1 and table 9-2. note 8: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see ta- ble 9-3. note 9: the clock "fc" can be selected as the source clock only in 8 bit pwm mode. table 9-1 operating mode and selectable source clock (normal1/2 and idle1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer - - - - - 8-bit event counter - - - - - - - 8-bit pdo - - - - - 8-bit pwm - - 16-bit timer - - - - - 16-bit event counter - - - - - - - - warm-up counter - - - - - - - - 16-bit pwm - 16-bit ppg - - - - note 1: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: : available source clock table 9-2 operating mode and selectable source clock (slow1/2 and sleep1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer - - - - - - - - 8-bit event counter - - - - - - - 8-bit pdo - - - - - - - - 8-bit pwm - - - - - - - 16-bit timer - - - - - - - - 16-bit event counter - - - - - - - - warm-up counter - - - - - - - - 16-bit pwm - - - - - - 16-bit ppg - - - - - - - note 1: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: : available source clock TMP86FH09AMG page 83
table 9-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg4, 3) 65535 warm-up counter 256 (ttreg4, 3) 65535 16-bit pwm 2 (pwreg4, 3) 65534 16-bit ppg 1 (pwreg4, 3) < (ttreg4, 3) 65535 and (pwreg4, 3) + 1 < (ttreg4, 3) note:n = 3 to 4 TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.2 timercounter control page 84
9.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (pdo), 8-bit pulse width modulation (pwm) output modes. the timercounter 3 and 4 (tc3, 4) are cascadable to form a 16-bit timer. the 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up coun- ter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 9.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-coun- ter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the timer mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect imme- diately after the programming. therefore, if ttregj is changed while the timer is running, an expected op- eration may not be obtained. note 3: j = 3, 4 table 9-4 source clock for timer counter 3, 4 (internal clock) source clock (note) resolution maximum setting time normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128 s 244.14 s 32.6 ms 62.3 ms fc/2 7 fc/2 7 - 8 s - 2.0 ms - fc/2 5 fc/2 5 - 2 s - 510 s - fc/2 3 fc/2 3 - 500 ns - 127.5 s - note:in the timer mode, do not select a source clock other than those shown above. example :setting the timer mode with source clock fc/2 7 hz and generating an interrupt 80 s later (timercounter4, fc = 16.0 mhz) ld (ttreg4), 0ah ; sets the timer register (80 s 2 7 /fc = 0ah). di set (eirh). 3 ; enables inttc4 interrupt. ei ld (tc4cr), 00010000b ; sets the operating clock to fc/2 7 , and 8-bit timer mode. ld (tc4cr), 00011000b ; starts tc4. TMP86FH09AMG page 85
figure 9-2 8-bit timer mode timing chart (tc4) 9.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj value is detected, an inttcj interrupt is gener- ated and the up-counter is cleared. after being cleared, the up-counter restarts counting at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may out- put pulses. note 2: in the event counter mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. note 3: j = 3, 4 figure 9-3 8-bit event counter mode timing chart (tc4) 9.3.3 8-bit programmable divider output (pdo) mode (tc3, 4) this mode is used to generate a pulse with a 50% duty cycle from the pdoj pin. in the pdo mode, the up-counter counts up using the internal clock. when a match between the up-coun- ter and the ttregj value is detected, the logic level output from the pdoj pin is switched to the opposite state and the up-counter is cleared. the inttcj interrupt request is generated at the time. the logic state oppo- site to the timer f/fj logic level is output from the pdoj pin. an arbitrary value can be set to the timer f/fj by tcjcr. upon reset, the timer f/fj value is initialized to 0. to use the programmable divider output, set the output latch of the i/o port to 1. TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 86 1 0 2 n-1 n 0 1 2 0 n ? counter match detect counter clear n-1 n 2 0 1 match detect counter clear tc4cr ttreg4 inttc4 interrupt request tc4 pin input 1 2 3 n-1 n 0 1 n-1 n 2 0 1 2 0 n ? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg4 inttc4 interrupt request
example :generating 1024 hz pulse using tc4 (fc = 16.0 mhz) setting port ld (ttreg4), 3dh ; 1/1024 2 7 /fc 2 = 3dh ld (tc4cr), 00010001b ; sets the operating clock to fc/2 7 , and 8-bit pdo mode. ld (tc4cr), 00011001b ; starts tc4. note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the programmable divider output mode, the new value program- med in ttregj is in effect immediately after programming. therefore, if ttregj is changed while the timer is run- ning, an expected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr setting upon stopping of the timer. example: fixing the pdoj pin to the high level when the timercounter is stopped clr (tcjcr).3 ; stops the timer. clr (tcjcr).7 ; sets the pdoj pin to the high level. note 3: j = 3, 4 TMP86FH09AMG page 87
figure 9-4 8-bit pdo mode timing chart (tc4) TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 88 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr tc4cr ttreg4 timer f/f4 pdo 4 pin inttc4 interrupt request
9.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the tim- er f/fj is switched to the opposite state. the counter continues counting. the logic level output from the tim- er f/fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr, positive and negative pulses can be gen- erated. upon reset, the timer f/fj is cleared to 0. (the logic level output from the pwmj pin is the opposite to the timer f/fj logic level.) since pwregj in the pwm mode is serially connected to the shift register, the value set to pwregj can be changed while the timer is running. the value set to pwregj during a run of the timer is shifted by the inttcj interrupt request and loaded into pwregj. while the timer is stopped, the value is shifted immediate- ly after the programming of pwregj. if executing the read instruction to pwregj during pwm output, the value in the shift register is read, but not the value set in pwregj. therefore, after writing to pwregj, the read- ing data of pwregj is previous value until inttcj is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwregj immediately after the inttcj interrupt request is generated (normally in the inttcj interrupt service routine.) if the programming of pwregj and the inter- rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next inttcj interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwmj pin holds the output status when the timer is stop- ped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr upon stopping of the timer. example: fixing the pwmj pin to the high level when the timercounter is stopped clr (tcjcr).3 ; stops the timer. clr (tcjcr).7 ; sets the pwmj pin to the high level. note 3: to enter the stop mode during pwm output, stop the timer and then enter the stop mode. if the stop mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the pwmj pin during the warm-up period time after exiting the stop mode. note 4: j = 3, 4 table 9-5 pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128 s 244.14 s 32.8 ms 62.5 ms fc/2 7 fc/2 7 - 8 s - 2.05 ms - fc/2 5 fc/2 5 - 2 s - 512 s - fc/2 3 fc/2 3 - 500 ns - 128 s - fs fs fs 30.5 s 30.5 s 7.81 ms 7.81 ms fc/2 fc/2 - 125 ns - 32 s - fc fc - 62.5 ns - 16 s - TMP86FH09AMG page 89
figure 9-5 8-bit pwm mode timing chart (tc4) TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 90 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr tc4cr pwreg4 timer f/f4 pwm 4 pin inttc4 interrupt request write to pwreg4 write to pwreg4
9.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr to 1, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter continues counting. program the lower byte and upper byte in this order in the timer register. (programming only the upper or lower byte should not be attempted.) note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj, and ppgj pins may output a pulse. note 2: in the timer mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect imme- diately after programming of ttregj. therefore, if ttregj is changed while the timer is running, an expec- ted operation may not be obtained. note 3: j = 3, 4 table 9-6 source clock for 16-bit timer mode source clock resolution maximum setting time normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 fs/2 3 128 s 244.14 s 8.39 s 16 s fc/2 7 fc/2 7 - 8 s - 524.3 ms - fc/2 5 fc/2 5 - 2 s - 131.1 ms - fc/2 3 fc/2 3 - 500 ns - 32.8 ms - example :setting the timer mode with source clock fc/2 7 [hz], and generating an interrupt 300 ms later (fc = 16.0 mhz) ldw (ttreg3), 927ch ; sets the timer register (300 ms 2 7 /fc = 927ch). di set (eirh). 3 ; enables inttc4 interrupt. ei ld (tc3cr), 13h ; sets the operating clock to fc/2 7 , and 16-bit timer mode ; (lower byte). ld (tc4cr), 04h ; sets the 16-bit timer mode (upper byte). ld (tc4cr), 0ch ; starts the timer. TMP86FH09AMG page 91
figure 9-6 16-bit timer mode timing chart (tc3 and tc4) 9.3.6 16-bit event counter mode (tc3 and 4) in the event counter mode, the up-counter counts up at the falling edge to the tc3 pin. the timercounter 3 and 4 are cascadable to form a 16-bit event counter. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr to 1, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at the falling edge of the input pulse to the tc3 pin. two machine cycles are required for the low- or high-level pulse input to the tc3 pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/ 2 4 in the slow1/2 or sleep1/2 mode. program the lower byte (ttreg3), and upper byte (ttreg4) in this order in the timer register. (programming only the upper or lower byte should not be attempted.) note 1: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the event counter mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect imme- diately after the programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. note 3: j = 3, 4 9.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the log- ic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the log- ic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the coun- ter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the pwm 4 pin is the opposite to the timer f/f4 logic level.) TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 92 1 0 2 3 mn-1 mn 0 1 mn-1 mn 2 0 1 2 0 n ? m ? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg3 (lower byte) inttc4 interrupt request ttreg4 (upper byte)
since pwreg4 and 3 in the pwm mode are serially connected to the shift register, the values set to pwreg4 and 3 can be changed while the timer is running. the values set to pwreg4 and 3 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg4 and 3. while the timer is stop- ped, the values are shifted immediately after the programming of pwreg4 and 3. set the lower byte (pwreg3) and upper byte (pwreg4) in this order to program pwreg4 and 3. (programming only the low- er or upper byte of the register should not be attempted.) if executing the read instruction to pwreg4 and 3 during pwm output, the values set in the shift register is read, but not the values set in pwreg4 and 3. therefore, after writing to the pwreg4 and 3, reading da- ta of pwreg4 and 3 is previous value until inttc4 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg4 and 3 immediately after the inttc4 interrupt re- quest is generated (normally in the inttc4 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in genera- tion of pulse different from the programmed value until the next inttc4 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not pro- gram tc4cr upon stopping of the timer. example: fixing the pwm 4 pin to the high level when the timercounter is stopped clr (tc4cr).3 ; stops the timer. clr (tc4cr).7 ; sets the pwm 4 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 9-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 s 244.14 s 8.39 s 16 s fc/2 7 fc/2 7 - 8 s - 524.3 ms - fc/2 5 fc/2 5 - 2 s - 131.1 ms - fc/2 3 fc/2 3 - 500 ns - 32.8 ms - fs fs fs 30.5 s 30.5 s 2 s 2 s fc/2 fc/2 - 125 ns - 8.2 ms - fc fc - 62.5 ns - 4.1 ms - example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h ; sets the pulse width. ld (tc3cr), 33h ; sets the operating clock to fc/2 3 , and 16-bit pwm output mode ; (lower byte). ld (tc4cr), 056h ; sets tff4 to the initial value 0, and 16-bit pwm signal ; generation mode (upper byte). ld (tc4cr), 05eh ; starts the timer. TMP86FH09AMG page 93
figure 9-7 16-bit pwm mode timing chart (tc3 and tc4) TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 94 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr tc4cr pwreg3 (lower byte) timer f/f4 pwm 4 pin inttc4 interrupt request pwreg4 (upper byte) write to pwreg4 write to pwreg4 write to pwreg3 write to pwreg3
9.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) this mode is used to generate pulses with up to 16-bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the ppg 4 pin is the opposite to the timer f/f4.) set the lower byte and upper byte in this order to program the timer register. (ttreg3 ttreg4, pwreg3 pwreg4) (programming only the upper or lower byte should not be attempted.) for ppg output, set the output latch of the i/o port to 1. example :generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h ; sets the pulse width. ldw (ttreg3), 8002h ; sets the cycle period. ld (tc3cr), 33h ; sets the operating clock to fc/2 3 , and16-bit ppg mode ; (lower byte). ld (tc4cr), 057h ; sets tff4 to the initial value 0, and 16-bit ; ppg mode (upper byte). ld (tc4cr), 05fh ; starts the timer. note 1: in the ppg mode, do not change the pwregi and ttregi settings while the timer is running. since pwregi and ttregi are not in the shift register configuration in the ppg mode, the new values programmed in pwre- gi and ttregi are in effect immediately after programming pwregi and ttregi. therefore, if pwregi and ttregi are changed while the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during ppg output, the ppg 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not change tc4cr upon stopping of the timer. example: fixing the ppg 4 pin to the high level when the timercounter is stopped clr (tc4cr).3 ; stops the timer clr (tc4cr).7 ; sets the ppg 4 pin to the high level note 3: i = 3, 4 TMP86FH09AMG page 95
figure 9-8 16-bit ppg mode timing chart (tc3 and tc4) TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 96 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr tc4cr pwreg3 (lower byte) timer f/f4 ppg 4 pin inttc4 interrupt request pwreg4 (upper byte) ttreg3 (lower byte) ttreg4 (upper byte)
9.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16-bit timercounter. the warm-up counter mode has two types of mode; switching from the high-fre- quency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fix tcicr to 0. if not fixed, the pdoi, pwmi and ppgi pins may out- put pulses. note 2: in the warm-up counter mode, only upper 8 bits of the timer register ttreg4 and 3 are used for match de- tection and lower 8 bits are not used. note 3: i = 3, 4 9.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) in this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. before starting the timer, set syscr2 to 1 to oscillate the low-frequency clock. when a match between the up-counter and the timer register (ttreg4, 3) value is detected after the tim- er is started by setting tc4cr to 1, the counter is cleared by generating the inttc4 interrupt re- quest. after stopping the timer in the inttc4 interrupt service routine, set syscr2 to 1 to switch the system clock from the high-frequency to low-frequency, and then clear of syscr2 to 0 to stop the high-frequency clock. table 9-8 setting time of low-frequency warm-up counter mode (fs = 32.768 khz) minimum time setting (ttreg4, 3 = 0100h) maximum time setting (ttreg4, 3 = ff00h) 7.81 ms 1.99 s example :after checking low-frequency clock oscillation stability with tc4 and 3, switching to the slow1 mode set (syscr2).6 ; syscr2 1 ld (tc3cr), 43h ; sets tff3=0, source clock fs, and 16-bit mode. ld (tc4cr), 05h ; sets tff4=0, and warm-up counter mode. ldw (ttreg3), 8000h ; sets the warm-up time. ; (the warm-up time depends on the oscillator characteristic.) di ; imf 0 set (eirh). 3 ; enables the inttc4. ei ; imf 1 set (tc4cr).3 ; starts tc4 and 3. : : pinttc4: clr (tc4cr).3 ; stops tc4 and 3. set (syscr2).5 ; syscr2 1 ; (switches the system clock to the low-frequency clock.) clr (syscr2).7 ; syscr2 0 (stops the high-frequency clock.) reti : : vinttc4: dw pinttc4 ; inttc4 vector table TMP86FH09AMG page 97
9.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stabil- ity is obtained. before starting the timer, set syscr2 to 1 to oscillate the high-frequency clock. when a match between the up-counter and the timer register (ttreg4, 3) value is detected after the tim- er is started by setting tc4cr to 1, the counter is cleared by generating the inttc4 interrupt re- quest. after stopping the timer in the inttc4 interrupt service routine, clear syscr2 to 0 to switch the system clock from the low-frequency to high-frequency, and then syscr2 to 0 to stop the low-frequency clock. table 9-9 setting time in high-frequency warm-up counter mode minimum time setting (ttreg4, 3 = 0100h) maximum time setting (ttreg4, 3 = ff00h) 16 s 4.08 ms example :after checking high-frequency clock oscillation stability with tc4 and 3, switching to the normal1 mode set (syscr2).7 ; syscr2 1 ld (tc3cr), 63h ; sets tff3=0, source clock fc, and 16-bit mode. ld (tc4cr), 05h ; sets tff4=0, and warm-up counter mode. ldw (ttreg3), 0f800h ; sets the warm-up time. ; (the warm-up time depends on the oscillator characteristic.) di ; imf 0 set (eirh). 3 ; enables the inttc4. ei ; imf 1 set (tc4cr).3 ; starts the tc4 and 3. : : pinttc4: clr (tc4cr).3 ; stops the tc4 and 3. clr (syscr2).5 ; syscr2 0 ; (switches the system clock to the high-frequency clock.) clr (syscr2).6 ; syscr2 0 ; (stops the low-frequency clock.) reti : : vinttc4: dw pinttc4 ; inttc4 vector table TMP86FH09AMG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 98
10. asynchronous serial interface (uart) 10.1 configuration figure 10-1 uart (asynchronous serial interface) TMP86FH09AMG page 99 counter s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2   noise rejection circuit   transmit control circuit shift register shift register receive control circuit mpx: multiplexer m p x y s a b c uartcr1 tdbuf rdbuf inttxd intrxd uartsr uartcr2 rxd txd inttc3
10.2 control uart is controlled by the uart control registers (uartcr1, uartcr2). the operating status can be moni- tored using the uart status register (uartsr). uart control register1 uartcr1 (0025h) 7 6 5 4 3 2 1 0 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 tc3 (input inttc3) fc/96 note 1: when operations are disabled by setting txe and rxe bit to 0, the setting becomes valid when data transmit or re- ceive complete. when the transmit data is stored in the transmit data buffer, the data are not transmitted. even if da- ta transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uartcr1 and uartcr1 should be set to 0 before uartcr1 is changed. TMP86FH09AMG 10. asynchronous serial interface (uart) 10.2 control page 100
uart control register2 uartcr2 (0026h) 7 6 5 4 3 2 1 0 rxdnc stopbr (initial value: **** *000) rxdnc selection of rxd input noise rejection time 00: 01: 10: 11: no noise rejection (hysteresis input) rejects pulses shorter than 31/fc [s] as noise rejects pulses shorter than 63/fc [s] as noise rejects pulses shorter than 127/fc [s] as noise write only stopbr receive stop bit length 0: 1: 1 bit 2 bits note:settings of rxdnc are limited depending on the transfer clock specified by brg. the combination "" is avail- able but please do not select the combination "-". the transfer clock is calculated by the following equation : transfer clock [hz] = timer/counter source clock [hz] ttreg3 set value brg setting transfer clock [hz] rxdnc setting 00 (no noise rejection) 01 (reject pulses shorter than 31/fc[s] as noise) 10 (reject pulses shorter than 63/fc[s] as noise) 11 (reject pulses shorter than 127/fc[s] as noise) 000 fc/13 - 110 (when the transfer clock gen- erated by inttc3 is the same as the right side col- umn) fc/8 - - - fc/16 - - fc/32 - the setting except the above uart status register uartsr (0025h) 7 6 5 4 3 2 1 0 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty note:when an inttxd is generated, tbep flag is set to "1" automatically. uart receive data buffer rdbuf (0027h) 7 6 5 4 3 2 1 0 read only (initial value: 0000 0000) TMP86FH09AMG page 101
uart transmit data buffer tdbuf (0027h) 7 6 5 4 3 2 1 0 write only (initial value: 0000 0000) TMP86FH09AMG 10. asynchronous serial interface (uart) 10.2 control page 102
10.3 transfer data format in uart, an one-bit start bit (low level), stop bit (bit length selectable at high level, by uartcr1), and parity (select parity in uartcr1; even- or odd-numbered parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 10-2 transfer data format figure 10-3 caution on changing transfer data format note: in order to switch the transfer data format, perform transmit operations in the above figure 10-3 sequence ex- cept for the initial setting. TMP86FH09AMG page 103 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1
10.4 transfer rate the baud rate of uart is set of uartcr1. the example of the baud rate are shown as follows. table 10-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 when tc3 is used as the uart transfer rate (when uartcr1 = 110), the transfer clock and trans- fer rate are determined as follows: transfer clock [hz] = tc3 source clock [hz] / ttreg3 setting value transfer rate [baud] = transfer clock [hz] / 16 10.5 data sampling method the uart receiver keeps sampling input using the clock selected by uartcr1 until a start bit is detec- ted in rxd pin input. rt clock starts detecting l level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bit(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to ma- jority rule (the data are the same twice or more out of three samplings). figure 10-4 data sampling method TMP86FH09AMG 10. asynchronous serial interface (uart) 10.4 transfer rate page 104 rt0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2  3 4 5 6 7 8 9 10 11 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
10.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 10.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 10.8 transmit/receive operation 10.8.1 data transmit operation set uartcr1 to 1. read uartsr to check uartsr = 1, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-clears uartsr, transfers the data to the transmit shift register and the data are sequentially output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit starts, transmit buf- fer empty flag uartsr is set to 1 and an inttxd interrupt is generated. while uartcr1 = 0 and from when 1 is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transmit does not start. 10.8.2 data receive operation set uartcr1 to 1. when data are received via the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a pari- ty bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag uartsr is set and an intrxd in- terrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the data are not transferred to rdbuf (re- ceive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting uartcr1 bit to 0, the setting becomes val- id when data receive is completed. however, if a framing error occurs in data receive, the receive-dis- abling setting may not become valid. if a framing error occurs, be sure to perform a re-receive opera- tion. TMP86FH09AMG page 105
10.9 status flag 10.9.1 parity error when parity determined using the receive data bits differs from the received parity bit, the parity error flag uartsr is set to 1. the uartsr is cleared to 0 when the rdbuf is read after reading the uartsr. figure 10-5 generation of parity error 10.9.2 framing error when 0 is sampled as the stop bit in the receive data, framing error flag uartsr is set to 1. the uartsr is cleared to 0 when the rdbuf is read after reading the uartsr. figure 10-6 generation of framing error 10.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to 1. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to 0 when the rdbuf is read after reading the uartsr. TMP86FH09AMG 10. asynchronous serial interface (uart) 10.9 status flag page 106 final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr.
figure 10-7 generation of overrun error note:receive operations are disabled until the overrun error flag uartsr is cleared. 10.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to 0 when the rdbuf is read after reading the uartsr. figure 10-8 generation of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun error flag which should have been cleared still remains set. 10.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, that is, when data in tdbuf are transferred to the trans- mit shift register and data transmit starts, transmit data buffer empty flag uartsr is set to 1. the uartsr is cleared to 0 when the tdbuf is written after reading the uartsr. TMP86FH09AMG page 107 final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr
figure 10-9 generation of transmit data buffer empty 10.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = 1), transmit end flag uartsr is set to 1. the uartsr is cleared to 0 when the data transmit is started af- ter writing the tdbuf. figure 10-10 generation of transmit end flag and transmit data buffer empty TMP86FH09AMG 10. asynchronous serial interface (uart) 10.9 status flag page 108 shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep.
11. serial expansion interface (sei) sei is one of the serial interfaces incorporated in the TMP86FH09AMG. it allows connection to peripheral devi- ces via full-duplex synchronous communication protocols. the TMP86FH09AMG contain one channel of sei. sei is connected with an external device through sclk, mosi, miso and the terminal ss. sclk, mosi, mi- so, and ss pins respectively are shared with p02, p03, p04 and p05. when using these ports as sclk, mosi, mi- so, or ss pins, set the each port output latch to 1. 11.1 features ? the master outputs the shift clock for only a data transfer period. ? the clock polarity and phase are programmable. ? the data is 8 bits long. ? msb or lsb-first can be selected. ? the programmable data and clock timing of sei can be connected to almost all synchronous serial periph- eral devices. refer to "11.5 sei transfer formats " . ? the transfer rate can be selected from the following four (master only): 4 mbps, 2 mbps, 1 mbps, or 250 kbps (when operating at 16 mhz) ? the error detection circuit supports the following functions: a. write collision detection: when the shift register is accessed for write during transfer b. overflow detection: when new data is received while the transfer-finished flag is set (slave only) note:mode fault detect function is not supported. make sure to set secr bit to "1" for disabling the mode fault detection. figure 11-1 sei (serial extended interface) TMP86FH09AMG page 109 sei control unit port control unit clock control unit shift register read buffer sei control register sei status register bit order selection clock selection 4, 8, 16, 64 divide miso mode mstr cpha cpol bos ser sef wcol sovf see mosi sclk ss sei data register address data sei interrupt (intsei1) internal sei clock
11.2 sei registers the sei interface has the sei control register (secr), sei status register (sesr), and sei data register (sedr) which are used to set up the sei system and enable/disable sei operation. 11.2.1 sei control register (secr) 7 6 5 4 3 2 1 0 secr (002ah) mode see bos mstr cpol cpha ser (initial value: 0000 0100) read-modify-write instruction are prohibited mode mode fault detection (note1) 0: enables mode fault detection 1: disables mode fault detection it is available in master mode only. (note: make sure to set bit to "1" for disabling mode fault de- tection r/w see sei operation (note2) 0: disables sei operation 1: enables sei operation bos bit order selection 0: transmitted beginning with the msb (bit 7) of sedr register 1: transmitted beginning with the lsb (bit 0) of sedr register mstr mode selection (note3) 0: sets sei for slave 1: sets sei for master cpol clock polarity 0: selects active-h clock. sclk remains l when idle. 1: selects active-l clock. sclk remains h when idle. cpha clock phase selects clock phase. for details, refer to section sei transfer for- mats. ser selects sei transfer rate 00: divide-by-4 01: divide-by-8 10: divide-by-16 11: divide-by-64 note 1: if mode fault detection is enabled, an interrupt is generated when the modf flag (sesr) is set. note 2: sei operation can only be disabled after transfer is completed. before the sei can be used, the each port con- trol register and output latch control must be set for the sei function (in case p0 port, p0outcr and p0dr). when using the sei as the master, set the secr bit to 1 (to enable sei operation) and then place trans- mit data in the sedr register. this initiates transmission/reception. note 3: master/slave settings must be made before enabling sei operation (this means that the secr bit must first be set before setting the secr bit to 1). 11.2.1.1 transfer rate (1) master mode (transfer rate = fc/internal clock divide ratio (unit: bps)) the table below shows the relationship between settings of the ser bit and transfer bit rates when the sei is operating as the master. table 11-1 sei transfer rate ser internal clock divide ratio of sei transfer rate when fc = 16 mhz 00 4 4 mbps 01 8 2 mbps 10 16 1 mbps 11 64 250 kbps TMP86FH09AMG 11. serial expansion interface (sei) 11.2 sei registers page 110
(2) slave mode when the sei is operating as a slave, the serial clock is input from the master and the setting of the ser bit has no effect. the maximum transfer rate is fc/4. note:take note of the following relationship between the serial clock speed and fc on the master side: 15.625 kbps transfer rate fc/4 bps example) 15.625 kbps transfer rate 4 mbps (fc = 16 mhz at v dd = 4.5 to 5.5 v) 15.625 kbps transfer rate 2 mbps (fc = 8 mhz at v dd = 2.7 to 5.5 v) 11.2.2 sei status register (sesr) 7 6 5 4 3 2 1 0 sesr (0028h) sef wcol sovf ? (initial value: 0000 ****) sef transfer-finished flag (note1) 0: transfer in progress 1: transfer completed read only wcol write collision error flag (note2) 0: no write collision error occurred 1: write collision error occurred sovf overflow error flag (slave) (note3) 0: no overflow occurred 1: overflow occurred note 1: the sef flag is automatically set at completion of transfer. the sef flag thus set is automatically cleared by read- ing the sesr register and accessing the sedr register. note 2: the wcol flag is automatically set by a write to the sedr register while transfer is in progress. writing to the sedr register during transfer has no effect. the wcol flag thus set is automatically cleared by reading the sesr register and accessing the sedr register. no interrupts are generated for reasons that the wcol flag is set. note 3: during master mode: this bit does not function; its data when read is 0. during slave mode: the sovf flag is automatically set when the device finishes reading the next data while the sef flag is set. the sovf flag thus set is automatically cleared by reading the sesr register and accessing the sedr register. the sovf flag also is cleared by a switchover to master mode. no interrupts are generated for reasons that the sovf flag is set. 11.2.3 sei data register (sedr) the sei data register (sedr) is used to send and receive data. when the sei is set for master, data trans- fer is initiated by writing to this sedr register. if the master device needs to write to the sedr register af- ter transfer began, always check to see by means of an interrupt or by polling that the sef flag (sesr) is set, before writing to the sedr register. 7 6 5 4 3 2 1 0 sedr (0029h) sed7 sed6 sed5 sed4 sed3 sed2 sed1 sed0 r/w (initial value: 0000 0000) TMP86FH09AMG page 111
11.3 sei operation during a sei transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simultane- ously. the serial clock synchronizes the timing at which information on the two serial data lines are shifted or sam- pled. slave device can be selected individually using the slave select pin ( ss pin). for unselected slave devices, da- ta on the sei bus cannot be taken in. when operating as the master devices, the ss pin can be used to indicate multiple-master bus connection. 11.3.1 controlling sei clock polarity and phase the sei clock allows its phase and polarity to be selected in software from four combinations available by using two bits, cpha and cpol (secr). the clock polarity is set by cpol to select between active-high or active-low (the transfer format is unaf- fected). the clock phase is set by cpha. the master device and the slave devices to communicate with must have the same clock phase and polarity. if multiple slave devices with different transfer formats exist on the same bus, the format can be changed to that of the slave device to which to transfer. table 11-2 clock phase and polarity cpha sei control register (secr 002ah) bit 2 cpol sei control register (secr 002ah) bit 3 11.3.2 sei data and clock timing the programmable data and clock timing of sei allows connection to almost all synchronous serial periph- eral devices. refer to section "11.5 sei transfer formats ". TMP86FH09AMG 11. serial expansion interface (sei) 11.3 sei operation page 112
11.4 sei pin functions the TMP86FH09AMG have four input/output pins associated with sei transfer. the functionality of each pin de- pends on the sei devices mode (master or slave). the sclk pin, mosi pin and miso pin of all sei devices are connected with the same name pin to each other. 11.4.1 sclk pin the sclk pin functions as an output pin when sei is set for master, or as an input pin when sei is set for slave. when sei is set for master, serial clock is output from the sclk pin to external devices. after the master starts transfer, eight serial clock pulses are output from the sclk pin only during transfer. when sei is set for slave, the sclk pin functions as an input pin. during data transfer between master and slave, device operation is synchronized by the serial clock output from the master. when the ss pin of the slave device is h, data is not taken in regardless of whether the serial clock is avail- able. for both master and slave devices, data is shifted in and out at a rising or falling edge of the serial clock, and is sampled at the opposite edge where the data is stable. the active edge is determined by sei transfer pro- tocols. note:noise in a slave devices sclk input may cause the device to operate erratically. 11.4.2 miso/mosi pins the miso and mosi pins are used for serial data transmission/reception. the status of each pin during mas- ter and slave are shown in the table below. table 11-3 miso/mosi pin status miso mosi master input output slave output input also, the sclk, mosi, and miso pins can be set for open-drain by the each pins input/output control reg- ister (in case p0 port, input/output control register is p0outcr). the miso pin of a slave device becomes an output when the secr bit is set to 1 (sei operation en- abled). to set the miso pin of an inactive slave device to a high-impedance state, clear the secr bit to 0. 11.4.3 ss pin the ss pin function differently when the sei is the master and when it is a slave. when the sei is a slave, this pin is used to enable the sei transmission/reception. when the slaves ss pin is high, the slave device ignores the serial clock from the master. nor does it receive data from the mi- so pin. when the slaves ss pin is l, the sei operates as slave. TMP86FH09AMG page 113
11.5 sei transfer formats the transfer formats are set using cpha and cpol (secr). cpha allows transfer protocols to be selected between two. 11.5.1 cpha (secr register bit 2) = 0 format figure 11-2 shows a transfer format where cpha = 0. figure 11-2 transfer format where cpha = 0 table 11-4 transfer format details where cpha = 0 sclk level when not communicating (idle) data shift data sampling cpol = 0 l level falling edge of transfer clock rising edge of transfer clock cpol = 1 h level rising edge of transfer clock falling edge of transfer clock ? in master mode, transfer is initiated by writing new data to the sedr register. at this time, the new data changes state on the mosi pin a half clock period before the shift clock starts pulsing. use bos (secr) to select whether the data should be shifted out beginning with the msb or lsb. the sef flag (sesr) is set after the last shift cycle. ? in slave mode, writing data to the sedr register is inhibited when the ss pin is l. a write dur- ing this period causes collision of writes, so that the wcol flag (sesr) is set. there- fore, when writing data to the sedr (sei data register) after the sef flag is set upon completion of transfer, make sure the ss pin goes h again before writing the next data to the sedr register. note:in slave mode, be careful not to write data while the sef flag is set and the ss pin remains l. 11.5.2 cpha = 1 format figure 11-3 shows a transfer format where cpha = 1. TMP86FH09AMG 11. serial expansion interface (sei) 11.5 sei transfer formats page 114 sclk cycle sclk (cpol = 0) sclk (cpol = 1) mosi miso ss sef 1 2 3 4 5 6 7 8 internal shift clock secr
figure 11-3 transfer format where cpha = 1 table 11-5 transfer format details where cpha = 1 sclk level when not communicating (idle) data shift data sampling cpol=0 l level rising edge of transfer clock falling edge of transfer clock cpol=1 h level falling edge of transfer clock rising edge of transfer clock ? in master mode, transfer is initiated by writing new data to the sedr register. the new data changes state on the mosi pin at the first edge of the shift clock. use bos (secr) to se- lect whether the data should be shifted out beginning with the msb or lsb. ? in slave mode, unlike in the case of cpha = 0 format, data can be written to the sedr (sei data reg- ister) regardless of whether the ss pin is l or h. in both master and slave modes, the sef flag (sesr) is set after the last shift cycle. writing data to the sedr register while data transfer is in progress causes collision of writes. therefore, wait until the sef flag is set before writing new data to the sedr register. TMP86FH09AMG page 115 sclk cycle sclk (cpol = 0) sclk (cpol = 1) mosi miso ss sef 1 2 3 4 5 6 7 8 internal shift clock secr
11.6 functional description figure 11-4 shows how the sei master and slave are connected. when the master device sends data from its mosi pin to a slave devices mosi pin, the slave device returns da- ta from its miso pin to the master devices miso pin. this means that data are exchanged between master and slave via full-duplex communication, with data output and input operations synchronized by the same clock sig- nal. after end of transfer, the transmit byte in 8 bit shift register is replaced with the receive byte. figure 11-4 master and slave connection in sei TMP86FH09AMG 11. serial expansion interface (sei) 11.6 functional description page 116 8-bit shift register sei clock ss 8-bit shift register mosi master slave miso sclk mosi miso sclk 5 v 0v ss
11.7 interrupt generation the sei for the TMP86FH09AMG uses intsei1. when the sesr changes state from 0 to 1, respec- tive interrupts is generated. table 11-6 sei interrupt sei interrupt channel 1 (intsei1) interrupt generated for sef 11.8 sei system errors the sei has the facility to detect following two system errors. ? write collision error: when the sedr register is accessed for write during transfer. ? overflow error: when the new data byte is shift in before the previous data byte is read in slave mode. 11.8.1 write collision error collision of writes occurs when an attempt is made to write to the sedr register while transfer is in pro- gress. because the sedr register is not configured as dual-buffers when sending data, a write to the sedr reg- ister directly results in writing to the sei shift register. therefore, writing to the sedr register while trans- fer is in progress causes a write collision error. in no case is data transfer stopped in the middle, so that the write data which caused a write collision error will not be written to the shift register. because slaves cannot control the timing at which the master starts a transfer, collision of writes normally occurs on the slave side. write collision errors do not normally occur on the master side because the master has the right to per- form a transfer at any time, but in view of sei logic both the master and slaves have the facility to detect write collision errors. a write collision error tends to occur on the slave side when the master shifts out data at a speed faster than that at which the slave processes the transferred data. more specifically, a write collision error occurs in cases where the slave transfers a new value to the sedr register when the master already started a shift cy- cle for the next byte. 11.8.2 overflow error the transfer bit rate on the sei bus is determined by the master. a high bit rate causes a problem that a slave cannot keep abreast with transfer from the master, because the master is shifting out data faster than can be processed by the slave. the sei module uses the sovf flag (sesr) to detect that data has over- flowed. the sovf flag is set in the following cases: ? when the sei module is set for slave ? when the old data byte remains to be read while a new data byte has been received when the sovf flag is set, the sedr register is overwritten with a new data byte. note:please carefully examine the communication processing routine and communication rate when design- ing your application system. TMP86FH09AMG page 117
11.9 bus driver protection ? one method to protect the device against latch-up due to collision of the bus drivers is the use of an open- drain option. this means changing the sei pins cmos outputs to the open-drain type, which is accomplish- ed by setting the sclk, mosi, and miso pins for open-drain individually by using the each port input/out- put control register. in this case, these pins must be provided with pull-up resistors external to the chip. ? when using the sei pins as cmos outputs, we recommend connecting them to the bus via resistors in or- der to protect the device against collision of drivers. however, be sure to select the appropriate resistance value which will not affect actual device operation (example: 1 to several k). TMP86FH09AMG 11. serial expansion interface (sei) 11.9 bus driver protection page 118
12. 10-bit ad converter (adc) the TMP86FH09AMG have a 10-bit successive approximation type ad converter. 12.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 12-1. it consists of control register adccr1 and adccr2, converted value register adcdr1 and adcdr2, a da converter, a sample-hold circuit, a comparator, and a successive comparison circuit. note:before using ad converter, set appropriate value to i/o port register combining a analog input port. for de- tails, see the section on "i/o ports". figure 12-1 10-bit ad converter TMP86FH09AMG page 119 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit vss vdd vdd ain0 ain5
12.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels and operation mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and controls the connection of the da converter (ladder re- sistor network). 3. ad converted value register 1 (adcdr1) this register used to store the digital value after being converted by the ad converter. 4. ad converted value register 2 (adcdr2) this register monitors the operating status of the ad converter. ad converter control register 1 adccr1 (000eh) 7 6 5 4 3 2 1 0 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved note 1: select analog input channel during ad converter stops (adcdr2 = "0"). note 2: when the analog input channel is all use disabling, the adccr1 should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog in- put port use as general input port. and for port near to analog input, do not input intense signaling of change. note 4: the adccr1 is automatically cleared to "0" after starting conversion. note 5: do not set adccr1 newly again during ad conversion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is gener- ated (e.g., interrupt handling routine). TMP86FH09AMG 12. 10-bit ad converter (adc) 12.2 register configuration page 120
note 6: after stop or slow/sleep mode are started, ad converter control register1 (adccr1) is all initialized and no da- ta can be written in this register. therefore, to use ad converter again, set the adccr1 newly after returning to nor- mal1 or normal2 mode. ad converter control register 2 adccr2 (000fh) 7 6 5 4 3 2 1 0 irefon "1" ack "0" (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select (refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved note 1: always set bit0 in adccr2 to "0" and set bit4 in adccr2 to "1". note 2: when a read instruction for adccr2, bit6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad converter control register2 (adccr2) is all initialized and no da- ta can be written in this register. therefore, to use ad converter again, set the adccr2 newly after returning to nor- mal1 or normal2 mode. table 12-1 ack setting and conversion time condition conversion time 16 mhz 8 mhz 4 mhz 2 mhz 10 mhz 5 mhz 2.5 mhz ack 000 39/fc - - - 19.5 s - - 15.6 s 001 reserved 010 78/fc - - 19.5 s 39.0 s - 15.6 s 31.2 s 011 156/fc - 19.5 s 39.0 s 78.0 s 15.6 s 31.2 s 62.4 s 100 312/fc 19.5 s 39.0 s 78.0 s 156.0 s 31.2 s 62.4 s 124.8 s 101 624/fc 39.0 s 78.0 s 156.0 s - 62.4 s 124.8 s - 110 1248/fc 78.0 s 156.0 s - - 124.8 s - - 111 reserved note 1: setting for "?" in the above table are inhibited. fc: high frequency oscillation clock [hz] note 2: set conversion time setting should be kept more than the following time by analog reference voltage (varef) . - varef = 4.5 to 5.5 v 15.6 s and more - varef = 2.7 to 5.5 v 31.2 s and more ad converted value register 1 adcdr1 (0021h) 7 6 5 4 3 2 1 0 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 (initial value: 0000 0000) TMP86FH09AMG page 121
ad converted value register 2 adcdr2 (0020h) 7 6 5 4 3 2 1 0 ad01 ad00 eocf adbf (initial value: 0000 ****) eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion note 1: the adcdr2 is cleared to "0" when reading the adcdr1. therefore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: the adcdr2 is set to "1" when ad conversion starts, and cleared to "0" when ad conversion finished. it al- so is cleared upon entering stop mode or slow mode. note 3: if a read instruction is executed for adcdr2, read data of bit3 to bit0 are unstable. TMP86FH09AMG 12. 10-bit ad converter (adc) 12.2 register configuration page 122
12.3 function 12.3.1 software start mode after setting adccr1 to 01 (software start mode), set adccr1 to 1. ad conver- sion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared after ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt han- dling routine). figure 12-2 software start mode 12.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeated- ly. in this mode, ad conversion is started by setting adccr1 to 1 after setting adccr1 to 11 (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is completed, the next ad conversion is started. to stop ad conversion, set adccr1 to 00 (disable mode) by writing 0s. the ad convert operation is stop- ped immediately. the converted value at this time is not stored in the ad converted value register. TMP86FH09AMG page 123 adcdr1 status eocf cleared by reading conversion result conversion result read adcdr2 intadc interrupt request adcdr2 adccr1 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdr1 a dcdr2 conversion result read conversion result read conversion result read
figure 12-3 repeat mode 12.3.3 register setting 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable for analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 12-1 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control regis- ter 1 (adccr1) to 1. if software start mode has been selected, ad conversion starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad conver- ted value register 1 (adcdr1) and the ad conversion finished flag (eocf) of ad converted val- ue register 2 (adcdr2) is set to 1, upon which time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to 0 by a read of the conversion result. however, if reconverted before a regis- ter read, although eocf is cleared the previous conversion result is retained until the next conver- sion is completed. TMP86FH09AMG 12. 10-bit ad converter (adc) 12.3 function page 124 a dcdr1,adcdr2 eocf cleared by reading conversion result conversion result read a dcdr2 intadc interrupt request conversion operation a dccr1 indeterminate ad conversion start adccr1 ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdr1 a dcdr2 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
example :after selecting the conversion time 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad conversion once. after checking eocf, read the converted value, store the lower 2 bits in address 0009eh and store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register appropriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccr1) , 00100011b ; select ain3 ld (adccr2) , 11011000b ;select conversion time(312/fc) and operation mode set (adccr1) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdr2) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdr2) ; read result data ld (9eh) , a ld a , (adcdr1) ; read result data ld (9fh), a 12.4 stop/slow modes during ad conversion when standby mode (stop or slow mode) is entered forcibly during ad conversion, the ad convert opera- tion is suspended and the ad converter is initialized (adccr1 and adccr2 are initialized to initial value). al- so, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (stop or slow mode).) when restored from stand- by mode (stop or slow mode), ad conversion is not automatically restarted, so it is necessary to restart ad con- version. note that since the analog reference voltage is automatically disconnected, there is no possibility of cur- rent flowing into the analog reference voltage. TMP86FH09AMG page 125
12.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit digital value converted by the ad as shown in figure 12-4. figure 12-4 analog input voltage and ad conversion result (typ.) TMP86FH09AMG 12. 10-bit ad converter (adc) 12.5 analog input voltage and ad conversion result page 126 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result vdd vss
12.6 precautions about ad converter 12.6.1 analog input pin voltage range make sure the analog input pins (ain0 to ain5) are used at voltages within vdd to vss. if any voltage out- side this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 12.6.2 analog input shared pins the analog input pins (ain0 to ain5) are shared with input/output ports. when using any of the analog in- puts to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversion from degrading. not only these analog input shared pins, some oth- er pins may also be affected by noise arising from input/output to and from adjacent pins. 12.6.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 12-5. the higher the output impe- dance of the analog input source, more easily they are susceptible to noise. therefore, make sure the output im- pedance of the signal source in your design is 5 k or less. toshiba also recommends attaching a capacitor ex- ternal to the chip. figure 12-5 analog input equivalent circuit and example of input pin processing TMP86FH09AMG page 127 da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k ? (typ) c = 12 pf (typ.) 5 k ? (max) note) i = 5 to 0
TMP86FH09AMG 12. 10-bit ad converter (adc) 12.6 precautions about ad converter page 128
13. key-on wakeup (kwu) TMP86FH09AMG have four pins p34 to p37, in addition to the p20 ( int5/ stop) pin, that can be used to exit stop mode. when using these p34 to p37 pins input to exit stop mode, pay attention to the logic of p20 pin. in details, re- fer to the following section"13.2 control". 13.1 configuration figure 13-1 key-on wakeup circuit figure 13-2 example of stop mode release operation TMP86FH09AMG page 129 stop mode release operation(p34 to 37) example of stop mode release operation "l" "h" "l" rising or falling edge detect stop wake-up* operation the time required for wakeup from releasing stop mode includes the warming-up time. for details, refer to section "control of operation modes". p3i * int5 p20 (int5/stop) p34 (ain2/stop2) p35 (ain3/stop3) stop mode release signal (1: release) stop mode control qd s stop2(stopcr) stop signal qd s stop3(stopcr) stop signal p36 (ain4/stop4) qd s stop4(stopcr) stop signal p37 (ain5/stop5) qd s stop5(stopcr) stop signal
13.2 control the p34 to p37 (stop2 to stop5) pins can individually be disabled/enabled using key-on wakeup control reg- ister (stopcr).when these pins are used as a release input of stop mode, beforehand they set to key-on wake- up by each register of p3 port. for details, refer to section "i/o ports". stop mode can be entered by setting up the system control register (syscr1), and can be released by detect- ing the active edge (rising or falling edge) on any stop2 to stop5 pins which are available for stop mode release. note:when using key-on wakeup function, select level mode ( set syscr1 to "1" ) for selection of stop mode release method. although p20 pin is shared with int5 and stop pin input, use mainly stop pin to release stop mode. this is because key-on wakeup function is comprised of stop pin and stop2 to stop5 pins as shown in the config- uration diagram. note 1: when stop mode release by an edge on stop pin, follow one of the two methods described below. (1) disable all of stop2 to stop5 pin inputs. (2) fix stop2 to 5 pin inputs high or low level. note 2: when using key-on wakeup (stop2 to 5 pins) to exit stop mode, make sure stop pin is held low and stop2 to 5 pin inputs are held high or low level, because stop mode release signal is created by or circuit the stop pin input and the stop2 to 5 pin input together. key-on wakeup stop mode control register stopcr 7 6 5 4 3 2 1 0 (0031h) stop5 stop4 stop3 stop2 (initial value : 0000 ****) stop2 stop mode release by p34 (stop2) 0: disable write only 1: enable stop3 stop mode release by p35 (stop3) 0: disable 1: enable stop4 stop mode release by p36 (stop4) 0: disable 1: enable stop5 stop mode release by p37 (stop5) 0: disable 1: enable the device is released from stop mode in the following condition. p20( stop) p3x stop mode release using p3x (stop2 to 5) level detection mode: low edge detection mode: disable edge detection rising or falling edge stop mode release using p20 ( stop) level detection mode: high edge detection mode: rising edge stopcr: inhibited note:assertion of the stop mode release signal is not recognized within three instruction cycles after executing the stop instruction. TMP86FH09AMG 13. key-on wakeup (kwu) 13.2 control page 130
14. flash memory TMP86FH09AMG has 16384byte flash memory (address: c000h to ffffh). the write and erase operations to the flash memory are controlled in the following three types of mode. - mcu mode the flash memory is accessed by the cpu control in the mcu mode. this mode is used for software bug correction and firmware change after shipment of the device since the write operation to the flash mem- ory is available by retaining the application behavior. - serial prom mode the flash memory is accessed by the cpu control in the serial prom mode. use of the serial inter- face (uart) enables the flash memory to be controlled by the small number of pins. TMP86FH09AMG in the serial prom mode supports on-board programming which enables users to program flash memory after the microcontroller is mounted on a user board. - parallel prom mode the parallel prom mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. high-speed access to the flash memory is available by con- trolling address and data signals directly. for the support of the program writer, please ask toshiba sales representative. in the mcu and serial prom modes, the flash memory control register (flscr) is used for flash memory con- trol. this chapter describes how to access the flash memory using the flash memory control register (flscr) in the mcu and serial prom modes. note 1: the 'read protect' described by data sheet of old edition was changed into 'security program'. TMP86FH09AMG page 131
14.1 flash memory control the flash memory is controlled via the flash memory control register (flscr) and flash memory standby con- trol resister (flsstb). flash memory control register flscr 7 6 5 4 3 2 1 0 (0fffh) flsmd "1" (initial value: 1100 ****) flsmd flash memory command sequence exe- cution control 1100: disable command sequence execution 0011: enable command sequence execution others: reserved r/w note 1: the command sequence of the flash memory can be executed only when flsmd="0011b". in other cases, any at- tempts to execute the command sequence are ineffective. note 2: flsmd must be set to either "1100b" or "0011b". note 3: bits 3 through 0 in flscr are always read as dont care. note 4: always set bit3 in flscr to "1". flash memory standby control register flsstb 7 6 5 4 3 2 1 0 (0fe9h) fstb (initial value: **** ***0) fstb flash memory standby control 0: disable the standby function. 1: enable the standby function. write only note 1: when fstb is set to 1, do not execute the read/write instruction to the flash memory because there is a possibility that the expected data is not read or the program is not operated correctly. if executing the read/write instruction, fstb is initialized to 0 automatically. note 2: if an interrupt is issued when fstb is set to 1, fstb is initialized to 0 automatically and then the vector area of the flash memory is read. note 3: if the idle0/1/2, sleep0/1/2 or stop mode is activated when fstb is set to 1, fstb is initialized to 0 automatical- ly. in the idle0/1/2, sleep0/1/2 or stop mode, the standby function operates regardless of fstb setting. 14.1.1 flash memory command sequence execution control (flscr) the flash memory can be protected from inadvertent write due to program error or microcontroller misoper- ation. this write protection feature is realized by disabling flash memory command sequence execution via the flash memory control register (write protect). to enable command sequence execution, set flscr to 0011b. to disable command sequence execution, set flscr to 1100b. after reset, flscr is initialized to 1100b to disable command sequence execution. normally, flscr should be set to 1100b except when the flash memory needs to be written or erased. 14.1.2 flash memory standby control (flsstb) low power consumption is enabled by cutting off the steady-state current of the flash memory. in the idle0/1/2, sleep0/1/2 or stop mode, the steady-state current of the flash memory is cut off automatically. when the program is executed in the ram area (without accessing the flash memory) in the normal 1/2 or slow1/2 mode, the current can be cut off by the control of the register. to cut off the steady-state cur- rent of the flash memory, set flsstb to 1 by the control program in the ram area. the proce- dures for controlling the flsstb register are explained below. (steps1 and 2 are controlled by the program in the flash memory, and steps 3 through 8 are controlled by the write control program executed in the ram area.) TMP86FH09AMG 14. flash memory 14.1 flash memory control page 132
1. transfer the control program of the flsstb register to the ram area. 2. jump to the ram area. 3. disable (di) the interrupt master enable flag (imf = 0). 4. set flsstb to 1. 5. execute the user program. 6. repeat step 5 until the return request to the flash memory is detected. 7. set flsstb to 0. 8. jump to the flash memory area. note 1: the standby function is not operated by setting flsstb with the program in the flash memory. you must set flsstb by the program in the ram area. note 2: to use the standby function by setting flsstb to 1 with the program in the ram area, flsstb must be set to 0 by the program in the ram area before returning the program control to the flash memory. if the program control is returned to the flash memory with flsstb set to 1, the pro- gram may malfunction and run out of control. TMP86FH09AMG page 133
14.2 command sequence the command sequence in the mcu and the serial prom modes consists of six commands (jedec compati- ble), as shown in table 14-1. addresses specified in the command sequence are recognized with the lower 12 bits (excluding ba, sa, and ff7fh used for security program). the upper 4 bits are used to specify the flash memo- ry area, table 14-1 command sequence command sequence 1st bus write cycle 2nd bus write cy- cle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle address data address data address data address data address data address data 1 byte program 555h aah aaah 55h 555h a0h ba (note 1) data (note 1) - - - - 2 sector erase (4-kbyte erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h sa (note 2) 30h 3 chip erase (all erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h 555h 10h 4 product id entry 555h aah aaah 55h 555h 90h - - - - - - 5 product id exit xxh f0h - - - - - - - - - - product id exit 555h aah aaah 55h 555h f0h - - - - - - 6 security program 555h aah aaah 55h 555h a5h ff7fh 00h - - - - note 1: set the address and data to be written. note 2: the area to be erased is specified with the upper 4 bits of the address. 14.2.1 byte program this command writes the flash memory for each byte unit. the addresses and data to be written are speci- fied in the 4th bus write cycle. each byte can be programmed in a maximum of 40 s. the next command se- quence cannot be executed until the write operation is completed. to check the completion of the write opera- tion, perform read operations repeatedly until the same data is read twice from the same address in the flash memory. during the write operation, any consecutive attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). note:to rewrite data to flash memory addresses at which data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 14.2.2 sector erase (4-kbyte erase) this command erases the flash memory in units of 4 kbytes. the flash memory area to be erased is speci- fied by the upper 4 bits of the 6th bus write cycle address. for example, to erase 4 kbytes from f000h to ffffh, specify one of the addresses in f000h-ffffh as the 6th bus write cycle. the sector erase command is effective only in the mcu and serial prom modes, and it cannot be used in the parallel prom mode. a maximum of 30 ms is required to erase 4 kbytes. the next command sequence cannot be executed until the erase operation is completed. to check the completion of the erase operation, perform read operations re- peatedly for data polling until the same data is read twice from the same address in the flash memory. dur- ing the erase operation, any consecutive attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). TMP86FH09AMG 14. flash memory 14.2 command sequence page 134
14.2.3 chip erase (all erase) this command erases the entire flash memory in approximately 30 ms. the next command sequence can- not be executed until the erase operation is completed. to check the completion of the erase operation, per- form read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory. during the erase operation, any consecutive attempts to read from the same address is re- versed bit 6 of the data (toggling between 0 and 1). after the chip is erased, all bytes contain ffh. 14.2.4 product id entry this command activates the product id mode. in the product id mode, the vendor id, the flash id, and the security program status can be read from the flash memory. table 14-2 values to be read in the product id mode address meaning read value f000h vendor id 98h f001h flash macro id 41h f002h flash size 0eh: 60 kbytes 0bh: 48 kbytes 07h: 32 kbytes 05h: 24 kbytes 03h: 16 kbytes 01h: 8 kbytes 00h: 4 kbytes ff7fh security program status ffh: security program disabled other than ffh: security program enabled note:the value at address f002h (flash size) depends on the size of flash memory incorporated in each product. for example, if the product has 60-kbyte flash memory, "0eh" is read from address f002h. 14.2.5 product id exit this command is used to exit the product id mode. 14.2.6 security program this command enables the read protection setting in the flash memory. when the security program is ena- bled, the flash memory cannot be read in the parallel prom mode. in the serial prom mode, the flash write and ram loader commands cannot be executed. to disable the security program setting, it is necessary to execute the chip erase command sequence. wheth- er or not the security program is enabled can be checked by reading ff7fh in the product id mode. for de- tails, see table 14-2. it takes a maximum of 40 s to set security program in the flash memory. the next command sequence can- not be executed until this operation is completed. to check the completion of the security program opera- tion, perform read operations repeatedly for data polling until the same data is read twice from the same ad- dress in the flash memory. during the security program operation, any attempts to read from the same ad- dress is reversed bit 6 of the data (toggling between 0 and 1). TMP86FH09AMG page 135
14.3 toggle bit (d6) after the byte program, chip erase, and security program command sequence is executed, any consecutive at- tempts to read from the same address is reversed bit 6 (d6) of the data (toggling between 0 and 1) until the opera- tion is completed. therefore, this toggle bit provides a software mechanism to check the completion of each opera- tion. usually perform read operations repeatedly for data polling until the same data is read twice from the same ad- dress in the flash memory. after the byte program, chip erase, or security program command sequence is execu- ted, the initial read of the toggle bit always produces a "1". TMP86FH09AMG 14. flash memory 14.3 toggle bit (d6) page 136
14.4 access to the flash memory area when the write, erase and security program are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. therefore, to perform these operations in the entire flash memory area, ac- cess to the flash memory area by the control program in the bootrom or ram area. (the flash memory pro- gram cannot write to the flash memory.) the serial prom or mcu mode is used to run the control program in the bootrom or ram area. note 1: the flash memory can be written or read for each byte unit. erase operations can be performed either in the en- tire area or in units of 4 kbytes, whereas read operations can be performed by an one transfer instruction. how- ever, the command sequence method is adopted for write and erase operations, requiring several-byte trans- fer instructions for each operation. note 2: to rewrite data to flash memory addresses at which data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 14.4.1 flash memory control in the serial prom mode the serial prom mode is used to access to the flash memory by the control program provided in the boot- rom area. since almost of all operations relating to access to the flash memory can be controlled simply by the communication data of the serial interface (uart), these functions are transparent to the user. for the de- tails of the serial prom mode, see serial prom mode. to access to the flash memory by using peripheral functions in the serial prom mode, run the ram load- er command to execute the control program in the ram area. the procedures to execute the control program in the ram area is shown in "14.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode)". 14.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) (steps 1 and 2 are controlled by the bootrom, and steps 3 through 9 are controlled by the control pro- gram executed in the ram area.) 1. transfer the write control program to the ram area in the ram loader mode. 2. jump to the ram area. 3. disable (di) the interrupt master enable flag (imf"0"). 4. set flscr to "0011b" (to enable command sequence execution). 5. execute the erase command sequence. 6. read the same flash memory address twice. (repeat step 6 until the same data is read by two consecutive reads operations.) 7. execute the write command sequence. 8. read the same flash memory address twice. (repeat step 8 until the same data is read by two consecutive reads operations.) 9. set flscr to "1100b" (to disable command sequence execution). note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: since the watchdog timer is disabled by the bootrom in the ram loader mode, it is not required to disable the watchdog timer by the ram loader program. TMP86FH09AMG page 137
example :after chip erasure, the program in the ram area writes data 3fh to address f000h. di : disable interrupts (imf"0") ld (flscr),00111000b : enable command sequence execution. ld ix,0f555h ld iy,0faaah ld hl,0f000h ; #### flash memory chip erase process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),80h : 3rd bus write cycle ld (ix),0aah : 4th bus write cycle ld (iy),55h : 5th bus write cycle ld (ix),10h : 6th bus write cycle sloop1: ld w,(hl) cmp w,(hl) jr nz,sloop1 : loop until the same value is read. ; #### flash memory write process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),0a0h : 3rd bus write cycle ld (hl),3fh : 4th bus write cycle, (f000h)=3fh sloop2: ld w,(hl) cmp w,(hl) jr nz,sloop2 : loop until the same value is read. ld (flscr),11001000b : disable command sequence execution. sloop3: jp sloop3 TMP86FH09AMG 14. flash memory 14.4 access to the flash memory area page 138
14.4.2 flash memory control in the mcu mode in the mcu mode, write operations are performed by executing the control program in the ram area. be- fore execution of the control program, copy the control program into the ram area or obtain it from the exter- nal using the communication pin. the procedures to execute the control program in the ram area in the mcu mode are described below. 14.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) (steps 1 and 2 are controlled by the program in the flash memory, and steps 3 through 11 are control- led by the control program in the ram area.) 1. transfer the write control program to the ram area. 2. jump to the ram area. 3. disable (di) the interrupt master enable flag (imf"0"). 4. disable the watchdog timer, if it is used. 5. set flscr to "0011b" (to enable command sequence execution). 6. execute the erase command sequence. 7. read the same flash memory address twice. (repeat step 7 until the same data is read by two consecutive read operations.) 8. execute the write command sequence. 9. read the same flash memory address twice. (repeat step 9 until the same data is read by two consecutive read operations.) 10. set flscr to "1100b" (to disable command sequence execution). 11. jump to the flash memory area. note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: when writing to the flash memory, do not intentionally use non-maskable interrupts (the watchdog tim- er must be disabled if it is used). if a non-maskable interrupt occurs while the flash memory is being written, unexpected data is read from the flash memory (interrupt vector), resulting in malfunction of the microcontroller. TMP86FH09AMG page 139
example :after sector erasure (e000h-efffh), the program in the ram area writes data 3fh to address e000h. di : disable interrupts (imf"0") ld (wdtcr2),4eh : clear the wdt binary counter. ldw (wdtcr1),0b101h : disable the wdt. ld (flscr),00111000b : enable command sequence execution. ld ix,0f555h ld iy,0faaah ld hl,0e000h ; #### flash memory sector erase process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),80h : 3rd bus write cycle ld (ix),0aah : 4th bus write cycle ld (iy),55h : 5th bus write cycle ld (hl),30h : 6th bus write cycle sloop1: ld w,(hl) cmp w,(hl) jr nz,sloop1 : loop until the same value is read. ; #### flash memory write process #### ld (ix),0aah : 1st bus write cycle ld (iy),55h : 2nd bus write cycle ld (ix),0a0h : 3rd bus write cycle ld (hl),3fh : 4th bus write cycle, (e000h)=3fh sloop2: ld w,(hl) cmp w,(hl) jr nz,sloop2 : loop until the same value is read. ld (flscr),11001000b : disable command sequence execution. jp xxxxh : jump to the flash memory area. example :this write control program reads data from address f000h and stores it to 98h in the ram area. ld a,(0f000h) : read data from address f000h. ld (98h),a : store data to address 98h. TMP86FH09AMG 14. flash memory 14.4 access to the flash memory area page 140
15. serial prom mode 15.1 outline the TMP86FH09AMG has a 2048 byte bootrom (mask rom) for programming to flash memory. the boot- rom is available in the serial prom mode, and controlled by test, boot and reset pins. communication is performed via uart. the serial prom mode has seven types of operating mode: flash memory writing, ram loader, flash memory sum output, product id code output, flash memory status output, flash memory eras- ing and flash memory security program setting. memory address mapping in the serial prom mode differs from that in the mcu mode. figure 15-1 shows memory address mapping in the serial prom mode. table 15-1 operating range in the serial prom mode parameter min max unit power supply 4.5 5.5 v high frequency (note) 2 16 mhz note:though included in above operating range, some of high frequencies are not supported in the serial prom mode. for details, refer to table 15-5. 15.2 memory mapping the figure 15-1 shows memory mapping in the serial prom mode and mcu mode. in the serial prom mode, the bootrom (mask rom) is mapped in addresses from 7800h to 7fffh. figure 15-1 memory address maps TMP86FH09AMG page 141 003fh 0000h 64 bytes 2048 bytes 0040h 7800h 7fffh c000h ffffh ffffh sfr ram dbr sfr ram dbr bootrom flash memory serial prom mode mcu mode 16384 bytes 003fh 0000h 64 bytes 0040h flash memory c000h 16384 bytes 0fffh 0fffh 512 bytes 128 bytes 128 bytes 023fh 0f80h 0f80h 512 bytes 023fh
15.3 serial prom mode setting 15.3.1 serial prom mode control pins to execute on-board programming, activate the serial prom mode. table 15-2 shows pin setting to acti- vate the serial prom mode. table 15-2 serial prom mode setting pin setting test pin high boot/rxd0 pin high reset pin note:the boot pin is shared with the uart communication pin (rxd0 pin) in the serial prom mode. this pin is used as uart communication pin after activating serial prom mode 15.3.2 pin function in the serial prom mode, txd0 (p03) and rxd0 (p02) are used as a serial interface pin. table 15-3 pin function in the serial prom mode pin name (serial prom mode) input/ output function pin name (mcu mode) txd0 output serial data output (note 1) p03 boot/rxd0 input/in- put serial prom mode control/serial data input p02 reset input serial prom mode control reset test input fixed to high test vdd power supply 4.5 to 5.5 v vss power supply 0 v i/o ports except p03, p02 i/o these ports are in the high-impedance state in the serial prom mode. the input level is fixed to the port inputs with a hardware feature to prevent overlap current. (the port inputs are inva- lid.) to make the port inputs valid, set the pin of the spcr register to 1 by the ram loader con- trol program. xin input self-oscillate with an oscillator. (note 2) xout output note 1: during on-board programming with other parts mounted on a user board, be careful no to affect these communica- tion control pins. note 2: operating range of high frequency in serial prom mode is 2 mhz to 16 mhz. TMP86FH09AMG 15. serial prom mode 15.3 serial prom mode setting page 142
figure 15-2 serial prom mode pin setting note 1: for connection of other pins, refer to "table 15-3 pin function in the serial prom mode". 15.3.3 example connection for on-board writing figure 15-3 shows an example connection to perform on-board wring. figure 15-3 example connection for on-board writing note 1: when other parts on the application board effect the uart communication in the serial prom mode, isolate these pins by a jumper or switch. note 2: when the reset control circuit on the application board effects activation of the serial prom mode, isolate the pin by a jumper or switch. note 3: for connection of other pins, refer to "table 15-3 pin function in the serial prom mode". TMP86FH09AMG page 143 serial prom mode mcu mode vdd test reset pc control pull-up level converter xin xout vss gnd external control board application board rc power-on reset circuit reset control other parts (note 1) (note 2) boot / rxd0 (p02) txd0 (p03) vdd(4.5v to 5.5v) serial prom mode mcu mode vdd test reset external contro pull-up xin xout vss gnd boot / rxd0 (p02) txd0 (p03) TMP86FH09AMG vdd(4.5 to 5.5v)
15.3.4 activating the serial prom mode the following is a procedure to activate the serial prom mode. "figure 15-4 serial prom mode tim- ing" shows a serial prom mode timing. 1. supply power to the vdd pin. 2. set the reset pin to low. 3. set the test pin and boot/rxd0 pins to high. 4. wait until the power supply and clock oscillation stabilize. 5. set the reset pin to high. 6. input the matching data (5ah) to the boot/rxd0 pin after setup sequence. for details of the set- up timing, refer to "15.16 uart timing". figure 15-4 serial prom mode timing TMP86FH09AMG 15. serial prom mode 15.3 serial prom mode setting page 144 vdd test(input) reset(input) program setup time for serial prom mode (rxsup) high level setting matching data don't care reset mode serial prom mode input boot/rxd0 (input)
15.4 interface specifications for uart the following shows the uart communication format used in the serial prom mode. to perform on-board programming, the communication format of the write controller must also be set in the same manner. the default baud rate is 9600 bps regardless of operating frequency of the microcontroller. the baud rate can be modified by transmitting the baud rate modification data shown in table 15-4 to TMP86FH09AMG. the ta- ble 15-5 shows an operating frequency and baud rate. the frequencies which are not described in table 15-5 can not be used. - baud rate (default): 9600 bps - data length: 8 bits - parity addition: none - stop bit: 1 bit table 15-4 baud rate modification data baud rate modification data 04h 05h 06h 07h 0ah 18h 28h baud rate (bps) 76800 62500 57600 38400 31250 19200 9600 table 15-5 operating frequency and baud rate in the serial prom mode (note 3) reference baud rate (bps) 76800 62500 57600 38400 31250 19200 9600 baud rate modification data 04h 05h 06h 07h 0ah 18h 28h ref. fre- quency (mhz) rating (mhz) baud rate (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) 1 2 1.91 to 2.10 - - - - - - - - - - - - 9615 +0.16 2 4 3.82 to 4.19 - - - - - - - - 31250 0.00 19231 +0.16 9615 +0.16 4.19 3.82 to 4.19 - - - - - - - - 32734 +4.75 20144 +4.92 10072 +4.92 3 4.9152 4.70 to 5.16 - - - - - - 38400 0.00 - - 19200 0.00 9600 0.00 5 4.70 to 5.16 - - - - - - 39063 +1.73 - - 19531 +1.73 9766 +1.73 4 6 5.87 to 6.45 - - - - - - - - - - - - 9375 -2.34 6.144 5.87 to 6.45 - - - - - - - - - - - - 9600 0.00 5 7.3728 7.05 to 7.74 - - - 57600 0.00 - - - - 19200 0.00 9600 0.00 6 8 7.64 to 8.39 - - 62500 0.00 - - 38462 +0.16 31250 0.00 19231 +0.16 9615 +0.16 7 9.8304 9.40 to 10.32 76800 0.00 - - - - 38400 0.00 - - 19200 0.00 9600 0.00 10 9.40 to 10.32 78125 +1.73 - - - - 39063 +1.73 - - 19531 +1.73 9766 +1.73 8 12 11.75 to 12.90 - - - - 57692 +0.16 - - 31250 0.00 18750 -2.34 9375 -2.34 12.288 11.75 to 12.90 - - - - 59077 +2.56 - - 32000 +2.40 19200 0.00 9600 0.00 12.5 11.75 to 12.90 - - 60096 -3.85 60096 +4.33 - - 30048 -3.85 19531 +1.73 9766 +1.73 9 14.7456 14.10 to 15.48 - - - - 57600 0.00 38400 0.00 - - 19200 0.00 9600 0.00 10 16 15.27 to 16.77 76923 +0.16 62500 0.00 - - 38462 +0.16 31250 0.00 19231 +0.16 9615 +0.16 note 1: ref. frequency and rating show frequencies available in the serial prom mode. though the frequency is suppor- ted in the serial prom mode, the serial prom mode may not be activated correctly due to the frequency difference in the external controller (such as personal computer) and oscillator, and load capacitance of communication pins. note 2: it is recommended that the total frequency difference is within 3% so that auto detection is performed correctly by the reference frequency. note 3: the external controller must transmit the matching data (5ah) repeatedly till the auto detection of baud rate is per- formed. this number indicates the number of times the matching data is transmitted for each frequency. TMP86FH09AMG page 145
15.5 operation command the eight commands shown in table 15-6 are used in the serial prom mode. after reset release, the TMP86FH09AMG waits for the matching data (5ah). table 15-6 operation command in the serial prom mode command data operating mode description 5ah setup matching data. execute this command after releasing the reset. f0h flash memory erasing erases the flash memory area (address c000h to ffffh). 30h flash memory writing writes to the flash memory area (address c000h to ffffh). 60h ram loader writes to the specified ram area (address 0050h to 023fh). 90h flash memory sum output outputs the 2-byte checksum upper byte and lower byte in this order for the entire area of the flash memory (address c000h to ffffh). c0h product id code output outputs the product id code (13-byte data). c3h flash memory status output outputs the status code (7-byte data) such as the security program condi- tion. fah flash memory security program setting enables the security program. 15.6 operation mode the serial prom mode has seven types of modes, that are (1) flash memory erasing, (2) flash memory writ- ing, (3) ram loader, (4) flash memory sum output, (5) product id code output, (6) flash memory status output and (7) flash memory security program setting modes. description of each mode is shown below. 1. flash memory erasing mode the flash memory is erased by the chip erase (erasing an entire flash area) or sector erase (erasing sec- tors in 4-kbyte units). the erased area is filled with ffh. when the security program is enabled, the sec- tor erase in the flash erasing mode can not be performed. to disable the security program, perform the chip erase. before erasing the flash memory, TMP86FH09AMG checks the passwords except a blank prod- uct. if the password is not matched, the flash memory erasing mode is not activated. 2. flash memory writing mode data is written to the specified flash memory address for each byte unit. the external controller must transmit the write data in the intel hex format (binary). if no error is encountered till the end record, TMP86FH09AMG calculates the checksum for the entire flash memory area (c000h to ffffh), and re- turns the obtained result to the external controller. when the security program is enabled, the flash memo- ry writing mode is not activated. in this case, perform the chip erase command beforehand in the flash mem- ory erasing mode. before activating the flash memory writing mode, TMP86FH09AMG checks the pass- word except a blank product. if the password is not matched, flash memory writing mode is not activated. 3. ram loader mode the ram loader transfers the data in intel hex format sent from the external controller to the internal ram. when the transfer is completed normally, the ram loader calculates the checksum. after transmit- ting the results, the ram loader jumps to the ram address specified with the first data record in order to execute the user program. when the security program is enabled, the ram loader mode is not activa- ted. in this case, perform the chip erase beforehand in the flash memory erasing mode. before activating the ram loader mode, TMP86FH09AMG checks the password except a blank product. if the password is not matched, flash ram loader mode is not activated. 4. flash memory sum output mode TMP86FH09AMG 15. serial prom mode 15.5 operation command page 146
the checksum is calculated for the entire flash memory area (c000h to ffffh), and the result is re- turned to the external controller. since the bootrom does not support the operation command to read the flash memory, use this checksum to identify programs when managing revisions of application pro- grams. 5. product id code output the code used to identify the product is output. the code to be output consists of 13-byte data, which in- cludes the information indicating the area of the rom incorporated in the product. the external control- ler reads this code, and recognizes the product to write. (in the case of TMP86FH09AMG, the addresses from c000h to ffffh become the rom area.) 6. flash memory status output mode the status of the area from ffe0h to ffffh, and the security program condition are output as 7-byte code. the external controller reads this code to recognize the flash memory status. 7. flash memory security program setting mode this mode disables reading the flash memory data in parallel prom mode. in the serial prom mode, the flash memory writing and ram loader modes are disabled. to disable the flash memory security pro- gram, perform the chip erase in the flash memory erasing mode. TMP86FH09AMG page 147
15.6.1 flash memory erasing mode (operating command: f0h) table 15-7 shows the flash memory erasing mode. table 15-7 flash memory erasing mode transfer byte transfer data from the external controller to TMP86FH09AMG baud rate transfer data from TMP86FH09AMG to the external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: no data transmitted 3rd byte 4th byte baud rate change data (table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (f0h) - modified baud rate modified baud rate - ok: echo back data (f0h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address bit 15 to 08 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address bit 07 to 00 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start address bit 15 to 08 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start address bit 07 to 00 (note 4, 5) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 15th byte : mth byte password string (note 4, 5) - modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted nth - 2 byte erase area specification (note 2) modified baud rate - nth - 1 byte - modified baud rate ok: checksum (upper byte) (note 3) error: nothing transmitted nth byte - modified baud rate ok: checksum (lower byte) (note 3) error: nothing transmitted nth + 1 byte (wait for the next operation command data) modified baud rate - note 1: xxh 3 indicates that the device enters the halt condition after transmitting 3 bytes of xxh. note 2: refer to "15.13 specifying the erasure area". note 3: refer to "15.8 checksum (sum)". note 4: refer to "15.10 passwords". note 5: do not transmit the password string for a blank product. note 6: when a password error occurs, TMP86FH09AMG stops uart communication and enters the halt mode. therefore, when a password error occurs, initialize TMP86FH09AMG by the reset pin and reactivate the serial prom mode. note 7: if an error occurs during transfer of a password address or a password string, TMP86FH09AMG stops uart commu- nication and enters the halt condition. therefore, when a password error occurs, initialize TMP86FH09AMG by the re- set pin and reactivate the serial prom mode. TMP86FH09AMG 15. serial prom mode 15.6 operation mode page 148
description of the flash memory erasing mode 1. the 1st through 4th bytes of the transmitted and received data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in the flash memory erasing mode (f0h). 3. when the 5th byte of the received data contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received da- ta (in this case, f0h). if the 5th byte of the received data does not contain the operation command da- ta, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 4. the 7th thorough m'th bytes of the transmitted and received data contain the same data as in the flash memory writing mode. in the case of a blank product, do not transmit a password string. (do not transmit a dummy password string.) 5. the nth - 2 byte contains the erasure area specification data. the upper 4 bits and lower 4 bits spec- ify the start address and end address of the erasure area, respectively. for the detailed description, see "15.13 specifying the erasure area". 6. the nth - 1 byte and nth byte contain the upper and lower bytes of the checksum, respectively. for how to calculate the checksum, refer to "15.8 checksum (sum)". checksum is calculated un- less a receiving error or intel hex format error occurs. after sending the end record, the external con- troller judges whether the transmission is completed correctly by receiving the checksum sent by the device. 7. after sending the checksum, the device waits for the next operation command data. TMP86FH09AMG page 149
15.6.2 flash memory writing mode (operation command: 30h) table 15-8 shows flash memory writing mode process. table 15-8 flash memory writing mode process transfer byte transfer data from external controller to TMP86FH09AMG baud rate transfer data from TMP86FH09AMG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (30h) - modified baud rate modified baud rate - ok: echo back data (30h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 15th byte : mth byte password string (note 5) - modified baud rate - ok: nothing transmitted error: nothing transmitted mth + 1 byte : nth - 2 byte intel hex format (binary) (note 2) modified baud rate - - nth - 1 byte - modified baud rate ok: sum (upper byte) (note 3) error: nothing transmitted nth byte - modified baud rate ok: sum (lower byte) (note 3) error: nothing transmitted nth + 1 byte (wait state for the next operation com- mand data) modified baud rate - note 1: xxh 3 indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to "15.7 er- ror code". note 2: refer to "15.9 intel hex format (binary)". note 3: refer to "15.8 checksum (sum)". note 4: refer to "15.10 passwords". note 5: if addresses from ffe0h to ffffh are filled with ffh, the passwords are not compared because the device is con- sidered as a blank product. transmitting a password string is not required. even in the case of a blank product, it is re- quired to specify the password count storage address and the password comparison start address. transmit these da- ta from the external controller. if a password error occurs due to incorrect password count storage address or pass- word comparison start address, TMP86FH09AMG stops uart communication and enters the halt condition. there- fore, when a password error occurs, initialize TMP86FH09AMG by the reset pin and reactivate the serial rom mode. note 6: if the security program is enabled or a password error occurs, TMP86FH09AMG stops uart communication and en- ters the halt condition. in this case, initialize TMP86FH09AMG by the reset pin and reactivate the serial rom mode. TMP86FH09AMG 15. serial prom mode 15.6 operation mode page 150
note 7: if an error occurs during the reception of a password address or a password string, TMP86FH09AMG stops uart com- munication and enters the halt condition. in this case, initialize TMP86FH09AMG by the reset pin and reactivate the serial prom mode. note 8: do not write only the address from ffe0h to ffffh when all flash memory data is the same. if only these area are writ- ten, the subsequent operation can not be executed due to password error. note 9: to rewrite data to flash memory addresses at which data (including ffh) is already written, make sure to erase the ex- isting data by "sector erase" or "chip erase" before rewriting data. description of the flash memory writing mode 1. the 1st byte of the received data contains the matching data. when the serial prom mode is activa- ted, TMP86FH09AMG (hereafter called device), waits to receive the matching data (5ah). upon re- ception of the matching data, the device automatically adjusts the uarts initial baud rate to 9600 bps. 2. when receiving the matching data (5ah), the device transmits an echo back data (5ah) as the sec- ond byte data to the external controller. if the device can not recognize the matching data, it does not transmit the echo back data and waits for the matching data again with automatic baud rate adjust- ment. therefore, the external controller should transmit the matching data repeatedly till the device transmits an echo back data. the transmission repetition count varies depending on the frequency of device. for details, refer to table 15-5. 3. the 3rd byte of the received data contains the baud rate modification data. the five types of baud rate modification data shown in table 15-4 are available. even if baud rate is not modified, the exter- nal controller should transmit the initial baud rate data (28h: 9600 bps). 4. only when the 3rd byte of the received data contains the baud rate modification data correspond- ing to the device's operating frequency, the device echoes back data the value which is the same da- ta in the 4th byte position of the received data. after the echo back data is transmitted, baud rate mod- ification becomes effective. if the 3rd byte of the received data does not contain the baud rate mod- ification data, the device enters the halts condition after sending 3 bytes of baud rate modification er- ror code (62h). 5. the 5th byte of the received data contains the command data (30h) to write the flash memory. 6. when the 5th byte of the received data contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received da- ta (in this case, 30h). if the 5th byte of the received data does not contain the operation command da- ta, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 7. the 7th byte contains the data for 15 to 8 bits of the password count storage address. when the da- ta received with the 7th byte has no receiving error, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. 8. the 9th byte contains the data for 7 to 0 bits of the password count storage address. when the data received with the 9th byte has no receiving error, the device does not send any data. if a receiving er- ror or password error occurs, the device does not send any data and enters the halt condition. 9. the 11th byte contains the data for 15 to 8 bits of the password comparison start address. when the data received with the 11th byte has no receiving error, the device does not send any data. if a re- ceiving error or password error occurs, the device does not send any data and enters the halt condition. 10. the 13th byte contains the data for 7 to 0 bits of the password comparison start address. when the da- ta received with the 13th byte has no receiving error, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. TMP86FH09AMG page 151
11. the 15th through mth bytes contain the password data. the number of passwords becomes the da- ta (n) stored in the password count storage address. the external password data is compared with n-byte data from the address specified by the password comparison start address. the external con- troller should send n-byte password data to the device. if the passwords do not match, the device en- ters the halt condition without returning an error code to the external controller. if the addresses from ffe0h to ffffh are filled with ffh, the passwords are not compared because the device is considered as a blank product. 12. the mth + 1 through nth - 2 bytes of the received data contain the binary data in the intel hex for- mat. no received data is echoed back to the external controller. after receiving the start mark (3ah for :) in the intel hex format, the device starts data record reception. therefore, the re- ceived data except 3ah is ignored until the start mark is received. after receiving the start mark, the device receives the data record, that consists of data length, address, record type, write data and checksum. since the device starts checksum calculation after receiving an end record, the external controller should wait for the checksum after sending the end record. if a receiving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external controller. 13. the nth - 1 and nth bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to "15.8 checksum (sum)". the checksum is calculated only when the end re- cord is detected and no receiving error or intel hex format error occurs. after sending the end re- cord, the external controller judges whether the transmission is completed correctly by receiving the checksum sent by the device. 14. after transmitting the checksum, the device waits for the next operation command data. TMP86FH09AMG 15. serial prom mode 15.6 operation mode page 152
15.6.3 ram loader mode (operation command: 60h) table 15-9 shows ram loader mode process. table 15-9 ram loader mode process transfer bytes transfer data from external control- ler to TMP86FH09AMG baud rate transfer data from TMP86FH09AMG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (60h) - modified baud rate modified baud rate - ok: echo back data (60h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start address bit 15 to 08 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start address bit 07 to 00 (note 4) modified baud rate - ok: nothing transmitted error: nothing transmitted 15th byte : mth byte password string (note 5) - modified baud rate - ok: nothing transmitted error: nothing transmitted mth + 1 byte : nth - 2 byte intel hex format (binary) (note 2) modified baud rate modified baud rate - - nth - 1 byte - modified baud rate ok: sum (upper byte) (note 3) error: nothing transmitted nth byte - modified baud rate ok: sum (lower byte) (note 3) error: nothing transmitted ram - the program jumps to the start address of ram in which the first transferred data is written. note 1: xxh 3 indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to "15.7 er- ror code". note 2: refer to "15.9 intel hex format (binary)". note 3: refer to "15.8 checksum (sum)". note 4: refer to "15.10 passwords". note 5: if addresses from ffe0h to ffffh are filled with ffh, the passwords are not compared because the device is con- sidered as a blank product. transmitting a password string is not required. even in the case of a blank product, it is re- quired to specify the password count storage address and the password comparison start address. transmit these da- ta from the external controller. if a password error occurs due to incorrect password count storage address or pass- word comparison start address, TMP86FH09AMG stops uart communication and enters the halt condition. there- fore, when a password error occurs, initialize TMP86FH09AMG by the reset pin and reactivate the serial rom mode. note 6: after transmitting a password string, the external controller must not transmit only an end record. if receiving an end re- cord after a password string, the device may not operate correctly. TMP86FH09AMG page 153
note 7: if the security program is enabled or a password error occurs, TMP86FH09AMG stops uart communication and en- ters the halt condition. in this case, initialize TMP86FH09AMG by the reset pin and reactivate the serial prom mode. note 8: if an error occurs during the reception of a password address or a password string, TMP86FH09AMG stops uart com- munication and enters the halt condition. in this case, initialize TMP86FH09AMG by the reset pin and reactivate the serial prom mode. note 9: to rewrite data to flash memory addresses at which data (including ffh) is already written, make sure to erase the ex- isting data by "sector erase" or "chip erase" before rewriting data. description of ram loader mode 1. the 1st through 4th bytes of the transmitted and received data contains the same data as in the flash memory writing mode. 2. in the 5th byte of the received data contains the ram loader command data (60h). 3. when the 5th byte of the received data contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position (in this case, 60h). if the 5th byte does not contain the operation command data, the device enters the halt condi- tion after sending 3 bytes of operation command error code (63h). 4. the 7th through mth bytes of the transmitted and received data contain the same data as in the flash memory writing mode. 5. the mth + 1 through nth - 2 bytes of the received data contain the binary data in the intel hex for- mat. no received data is echoed back to the external controller. after receiving the start mark (3ah for :) in the intel hex format, the device starts data record reception. therefore, the re- ceived data except 3ah is ignored until the start mark is received. after receiving the start mark, the device receives the data record, that consists of data length, address, record type, write data and checksum. the writing data of the data record is written into ram specified by address. since the de- vice starts checksum calculation after receiving an end record, the external controller should wait for the checksum after sending the end record. if a receiving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external controller. 6. the nth - 1 and nth bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to "15.8 checksum (sum)". the checksum is calculated only when the end re- cord is detected and no receiving error or intel hex format error occurs. after sending the end re- cord, the external controller judges whether the transmission is completed correctly by receiving the checksum sent by the device. 7. after transmitting the checksum to the external controller, the boot program jumps to the ram ad- dress that is specified by the first received data record. TMP86FH09AMG 15. serial prom mode 15.6 operation mode page 154
15.6.4 flash memory sum output mode (operation command: 90h) table 15-10 shows flash memory sum output mode process. table 15-10 flash memory sum output process transfer bytes transfer data from external control- ler to TMP86FH09AMG baud rate transfer data from TMP86FH09AMG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (90h) - modified baud rate modified baud rate - ok: echo back data (90h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte - modified baud rate ok: sum (upper byte) (note 2) error: nothing transmitted 8th byte - modified baud rate ok: sum (lower byte) (note 2) error: nothing transmitted 9th byte (wait for the next operation com- mand data) modified baud rate - note 1: xxh 3 indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to "15.7 er- ror code". note 2: refer to "15.8 checksum (sum)". description of the flash memory sum output mode 1. the 1st through 4th bytes of the transmitted and received data contains the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in the flash memory sum output mode (90h). 3. when the 5th byte of the received data contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received da- ta (in this case, 90h). if the 5th byte of the received data does not contain the operation command da- ta, the device enters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th and the 8th bytes contain the upper and lower bits of the checksum, respectively. for how to calculate the checksum, refer to "15.8 checksum (sum)". 5. after sending the checksum, the device waits for the next operation command data. TMP86FH09AMG page 155
15.6.5 product id code output mode (operation command: c0h) table 15-11 shows product id code output mode process. table 15-11 product id code output process transfer bytes transfer data from external controller to TMP86FH09AMG baud rate transfer data from TMP86FH09AMG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (c0h) - modified baud rate modified baud rate - ok: echo back data (c0h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte modified baud rate 3ah start mark 8th byte modified baud rate 0ah the number of transfer data (from 9th to 18th bytes) 9th byte modified baud rate 02h length of address (2 bytes) 10th byte modified baud rate 1dh reserved data 11th byte modified baud rate 00h reserved data 12th byte modified baud rate 00h reserved data 13th byte modified baud rate 00h reserved data 14th byte modified baud rate 01h rom block count (1 block) 15th byte modified baud rate c0h first address of rom (upper byte) 16th byte modified baud rate 00h first address of rom (lower byte) 17th byte modified baud rate ffh end address of rom (upper byte) 18th byte modified baud rate ffh end address of rom (lower byte) 19th byte modified baud rate 22h checksum of transferred data (9th through 18th byte) 20th byte (wait for the next operation command data) modified baud rate - note:xxh 3 indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to "15.7 error code". description of product id code output mode 1. the 1st through 4th bytes of the transmitted and received data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the product id code output mode command data (c0h). TMP86FH09AMG 15. serial prom mode 15.6 operation mode page 156
3. when the 5th byte contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, c0h). if the 5th byte data does not contain the operation command data, the device enters the halt con- dition after sending 3 bytes of operation command error code (63h). 4. the 9th through 19th bytes contain the product id code. for details, refer to "15.11 product id code". 5. after sending the checksum, the device waits for the next operation command data. TMP86FH09AMG page 157
15.6.6 flash memory status output mode (operation command: c3h) table 15-12 shows flash memory status output mode process. table 15-12 flash memory status output mode process transfer bytes transfer data from external con- troller to TMP86FH09AMG baud rate transfer data from TMP86FH09AMG to ex- ternal controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (c3h) - modified baud rate modified baud rate - ok: echo back data (c3h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte modified baud rate 3ah start mark 8th byte modified baud rate 04h byte count (from 9th to 12th byte) 9th byte modified baud rate 00h to 03h status code 1 10th byte modified baud rate 00h reserved data 11th byte modified baud rate 00h reserved data 12th byte modified baud rate 00h reserved data 13th byte modified baud rate checksum 2s complement for the sum of 9th through 12th bytes 9th byte checksum 00h: 00h 01h: ffh 02h: feh 03h: fdh 14th byte (wait for the next operation com- mand data) modified baud rate - note 1: xxh 3 indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to "15.7 er- ror code". note 2: for the details on status code 1, refer to "15.12 flash memory status code". description of flash memory status output mode 1. the 1st through 4th bytes of the transmitted and received data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the flash memory status output mode command data (c3h). 3. when the 5th byte contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, c3h). if the 5th byte does not contain the operation command data, the device enters the halt condi- tion after sending 3 bytes of operation command error code (63h). 4. the 9th through 13th bytes contain the status code. for details on the status code, refer to "15.12 flash memory status code". TMP86FH09AMG 15. serial prom mode 15.6 operation mode page 158
5. after sending the status code, the device waits for the next operation command data. TMP86FH09AMG page 159
15.6.7 flash memory security program setting mode (operation command: fah) table 15-13 shows flash memory security program setting mode process. table 15-13 flash memory security program setting mode process transfer bytes transfer data from external con- troller to TMP86FH09AMG baud rate transfer data from TMP86FH09AMG to ex- ternal controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (fah) - modified baud rate modified baud rate - ok: echo back data (fah) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte password count storage address 15 to 08 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 9th byte 10th byte password count storage address 07 to 00 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 11th byte 12th byte password comparison start ad- dress 15 to 08 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 13th byte 14th byte password comparison start ad- dress 07 to 00 (note 2) modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted 15th byte : mth byte password string (note 2) - modified baud rate modified baud rate - ok: nothing transmitted error: nothing transmitted nth byte - modified baud rate ok: fbh (note 3) error: nothing transmitted n+1th byte (wait for the next operation com- mand data) modified baud rate - note 1: xxh 3 indicates that the device enters the halt condition after sending 3 bytes of xxh. for details, refer to "15.7 er- ror code". note 2: refer to "15.10 passwords". note 3: if the security program is enabled for a blank product or a password error occurs for a non-blank product, TMP86FH09AMG stops uart communication and enters the halt mode. in this case, initialize TMP86FH09AMG by the reset pin and reactivate the serial prom mode. note 4: if an error occurs during reception of a password address or a password string, TMP86FH09AMG stops uart commu- nication and enters the halt mode. in this case, initialize TMP86FH09AMG by the reset pin and reactivate the seri- al prom mode. description of the flash memory security program setting mode 1. the 1st through 4th bytes of the transmitted and received data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in the flash memory status output mode (fah). TMP86FH09AMG 15. serial prom mode 15.6 operation mode page 160
3. when the 5th byte of the received data contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received da- ta (in this case, fah). if the 5th byte does not contain the operation command data, the device en- ters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th through mth bytes of the transmitted and received data contain the same data as in the flash memory writing mode. 5. the n'th byte contains the status to be transmitted to the external controller in the case of the success- ful security program. TMP86FH09AMG page 161
15.7 error code when detecting an error, the device transmits the error code to the external controller, as shown in table 15-14. table 15-14 error code transmit data meaning of error data 62h, 62h, 62h baud rate modification error. 63h, 63h, 63h operation command error. a1h, a1h, a1h framing error in the received data. a3h, a3h, a3h overrun error in the received data. note:if a password error occurs, TMP86FH09AMG does not transmit an error code. 15.8 checksum (sum) 15.8.1 calculation method the checksum (sum) is calculated with the sum of all bytes, and the obtained result is returned as a word. the data is read for each byte unit and the calculated result is returned as a word. example: a1h if the data to be calculated consists of the four bytes, the checksum of the data is as shown below. b2h a1h + b2h + c3h + d4h = 02eah sum (high)= 02h sum (low)= eah c3h d4h the checksum which is transmitted by executing the flash memory write command, ram loader com- mand, or flash memory sum output command is calculated in the manner, as shown above. TMP86FH09AMG 15. serial prom mode 15.7 error code page 162
15.8.2 calculation data the data used to calculate the checksum is listed in table 15-15. table 15-15 checksum calculation data operating mode calculation data description flash memory writing mode data in the entire area of the flash memory even when a part of the flash memory is written, the check- sum of the entire flash memory area (c000h to fffh) is cal- culated. the data length, address, record type and checksum in intel hex format are not included in the checksum. flash memory sum output mode ram loader mode ram data written in the first received ram ad- dress through the last received ram address the length of data, address, record type and checksum in in- tel hex format are not included in the checksum. product id code output mode 9th through 18th bytes of the transferred data for details, refer to "15.11 product id code". flash memory status output mode 9th through 12th bytes of the transferred data for details, refer to "15.12 flash memory status code" flash memory erasing mode all data in the erased area of the flash memo- ry (the whole or part of the flash memory) when the sector erase is executed, only the erased area is used to calculate the checksum. in the case of the chip erase, an entire area of the flash memory is used. TMP86FH09AMG page 163
15.9 intel hex format (binary) 1. after receiving the checksum of a data record, the device waits for the start mark (3ah :) of the next da- ta record. after receiving the checksum of a data record, the device ignores the data except 3ah transmit- ted by the external controller. 2. after transmitting the checksum of end record, the external controller must transmit nothing, and wait for the 2-byte receive data (upper and lower bytes of the checksum). 3. if a receiving error or intel hex format error occurs, the device enters the halt condition without return- ing an error code to the external controller. the intel hex format error occurs in the following case: when the record type is not 00h, 01h, or 02h when a checksum error occurs when the data length of an extended record (record type = 02h) is not 02h when the device receives the data record after receiving an extended record (record type = 02h) with ex- tended address of 1000h or larger. when the data length of the end record (record type = 01h) is not 00h 15.10 passwords the consecutive eight or more-byte data in the flash memory area can be specified to the password. TMP86FH09AMG compares the data string specified to the password with the password string transmitted from the external controller. the area in which passwords can be specified is located at addresses c000h to ff9fh. the area from ffa0h to ffffh can not be specified as the passwords area. if addresses from ffe0h through ffffh are filled with ffh, the passwords are not compared because the prod- uct is considered as a blank product. even in this case, the password count storage addresses and password compar- ison start address must be specified. table 15-16 shows the password setting in the blank product and non-blank prod- uct. table 15-16 password setting in the blank product and non-blank product password blank product (note 1) non-blank product pnsa (password count storage address) c000h pnsa ff9fh c000h pnsa ff9fh pcsa (password comparison start address) c000h pcsa ff9fh c000h pcsa ffa0 ? n n (password count) * 8 n password string setting not required (note 5) required (note 2) note 1: when addresses from ffe0h through ffffh are filled with ffh, the product is recognized as a blank product. note 2: the data including the same consecutive data (three or more bytes) can not be used as a password. (this causes a password error data. TMP86FH09AMG transmits no data and enters the halt condition.) note 3: *: dont care. note 4: when the above condition is not met, a password error occurs. if a password error occurs, the device enters the halt condition without returning the error code. note 5: in the flash memory writing mode or ram loader mode, the blank product receives the intel hex format data immediate- ly after receiving pcsa without receiving password strings. in this case, the subsequent processing is performed cor- rectly because the blank product ignores the data except the start mark (3ah :) as the intel hex format data, even if the external controller transmits the dummy password string. however, if the dummy password string contains 3ah, it is detected as the start mark erroneously. the microcontroller enters the halt mode. if this causes the prob- lem, do not transmit the dummy password strings. note 6: in the flash memory erasing mode, the external controller must not transmit the password string for the blank product. TMP86FH09AMG 15. serial prom mode 15.9 intel hex format (binary) page 164
figure 15-5 password comparison 15.10.1 password string the password string transmitted from the external controller is compared with the specified data in the flash memory. when the password string is not matched to the data in the flash memory, the device enters the halt condition due to the password error. 15.10.2 handling of password error if a password error occurs, the device enters the halt condition. in this case, reset the device to reactivate the serial prom mode. 15.10.3 password management during program development if a program is modified many times in the development stage, confusion may arise as to the password. there- fore, it is recommended to use a fixed password in the program development stage. example :specify pnsa to f000h, and the password string to 8 bytes from address f001h (pcsa becomes f001h.) password section code abs = 0f000h db 08h : pnsa definition db code1234 : password string definition TMP86FH09AMG page 165 08h 01h 02h 03h 04h 05h 08h f012h f107h f108h flash memory f109h f10ah f10bh f10ch uart f0h 12h f1h 07h 01h 02h 03h 04h 05h 06h 07h 08h pnsa pcsa password string 06h 07h f10dh f10eh "08h" becomes the umber of passwords 8 bytes compare example pnsa = f012h pcsa = f107h password string = 01h,02h,03h,04h,05h 06h,07h,08h rxd pin
15.11 product id code the product id code is the 13-byte data containing the start address and the end address of rom. table 15-17 shows the product id code format. table 15-17 product id code format data description in the case of TMP86FH09AMG 1st start mark (3ah) 3ah 2nd the number of transfer data (10 bytes from 3rd to 12th byte) 0ah 3rd address length (2 bytes) 02h 4th reserved data 1dh 5th reserved data 00h 6th reserved data 00h 7th reserved data 00h 8th rom block count 01h 9th the first address of rom (upper byte) c0h 10th the first address of rom (lower byte) 00h 11th the end address of rom (upper byte) ffh 12th the end address of rom (lower byte) ffh 13th checksum of the transferred data (2s compliment for the sum of 3rd through 12th bytes) 22h 15.12 flash memory status code the flash memory status code is the 7-byte data including the security program status and the status of the data from ffe0h to ffffh. table 15-18 shows the flash memory status code. table 15-18 flash memory status code data description in the case of TMP86FH09AMG 1st start mark 3ah 2nd transferred data count (3rd through 6th byte) 04h 3rd status code 00h to 03h (see figure below) 4th reserved data 00h 5th reserved data 00h 6th reserved data 00h 7th checksum of the transferred data (2s compliment for the sum of 3rd through 6th data) 3rd byte 00h 01h 02h 03h checksum 00h ffh feh fdh TMP86FH09AMG 15. serial prom mode 15.11 product id code page 166
status code 1 7 6 5 4 3 2 1 0 rpena blank (initial value: 0000 00**) rpena flash memory security program status 0: 1: security program is disabled. security program is enabled. blank the status from ffe0h to ffffh. 0: 1: all data is ffh in the area from ffe0h to ffffh. the value except ffh is included in the area from ffe0h to ffffh. some operation commands are limited by the flash memory status code 1. if the security program is enabled, flash memory writing mode command and ram loader mode command can not be executed. erase all flash mem- ory before executing these command. rpena blank flash memory writing mode ram loader mode flash memory sum output mode product id code output mode flash memory status output mode flash memory erasing mode security pro- gram setting mode chip erase sector erase 0 0 0 1 pass pass pass pass 1 0 1 1 pass pass note:: the command can be executed. pass: the command can be executed with a password. : the command can not be executed. (after echoing the command back to the external controller, TMP86FH09AMG stops uart communication and enters the halt condition.) TMP86FH09AMG page 167
15.13 specifying the erasure area in the flash memory erasing mode, the erasure area of the flash memory is specified by n?2 byte data. the start address of an erasure area is specified by erasta, and the end address is specified by eraend. if erasta is equal to or smaller than eraend, the sector erase (erasure in 4 kbyte units) is executed. execut- ing the sector erase while the security program is enabled results in an infinite loop. if erasta is larger than eraend, the chip erase (erasure of an entire flash memory area) is executed and the security program is disabled. therefore, execute the chip erase (not sector erase) to disable the security program. erasure area specification data (n?2 byte data) 7 6 5 4 3 2 1 0 erasta eraend erasta the start address of the erasure area 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: from 0000h from 1000h from 2000h from 3000h from 4000h from 5000h from 6000h from 7000h from 8000h from 9000h from a000h from b000h from c000h from d000h from e000h from f000h eraend the end address of the erasure area 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: to 0fffh to 1fffh to 2fffh to 3fffh to 4fffh to 5fffh to 6fffh to 7fffh to 8fffh to 9fffh to afffh to bfffh to cfffh to dfffh to efffh to ffffh note:when the sector erase is executed for the area containing no flash cell, TMP86FH09AMG stops the uart com- munication and enters the halt condition. 15.14 port input control register in the serial prom mode, the input level is fixed to the all ports except p03 and p02 ports with a hardware fea- ture to prevent overlap current to unused ports. (all port inputs and peripheral function inputs shared with the ports become invalid.) therefore, to access to the flash memory in the ram loader mode without uart communi- cation, port inputs must be valid. to make port inputs valid, set the pin of the port input control register (spcr) to 1. the spcr register is not operated in the mcu mode. TMP86FH09AMG 15. serial prom mode 15.13 specifying the erasure area page 168
port input control register spcr (0feah) 7 6 5 4 3 2 1 0 pin (initial value: **** ***0) pin port input control in the serial prom mode 0: invalid port inputs (the input level is fixed with a hardware feature.) 1: valid port inputs r/w note 1: the spcr register can be read or written only in the serial prom mode. when the write instruction is executed to the spcr register in the mcu mode, the port input control can not be performed. when the read instruction is execu- ted for the spcr register in the mcu mode, read data of bit7 to 1 are unstable. note 2: all i/o ports except p03 and p02 ports are controlled by the spcr register. TMP86FH09AMG page 169
15.15 flowchart TMP86FH09AMG 15. serial prom mode 15.15 flowchart page 170 start setup receive uart data receive data = 5ah adjust the baud rate (adjust the source clock to 9600 bps) no yes transmit uart data (transmit data = 5ah) receive uart data modify the baud rate based on the receive data receive data = 30h (flash memory writing mode) receive data = 60h (ram loader mode) receive uart data (intel hex format) transmit uart data (checksum of an entire area) receive uart data transmit uart data (transmit data = 60h) receive uart data (intel hex format) jump to the start address of ram program transmit uart data (checksum of an entire area) receive data = c0h (product id code output mode) transmit uart data (transmit data = c0h) flash memory write process ram write process transmit uart data (product id code) transmit uart data (echo back the baud rate modification data) verify the password (compare the receive data and flash memory data) security program check security disabled security program check security disabled infinite loop infinite loop ng security enable ng receive data = c3h (flash memory status output mode) transmit uart data (transmit data = c3h) receive data = f0h (flash memory erasing mode) transmit uart data (transmit data = f0h) infinite loop ng chip erase (erase on entire area) transmit uart data (checksum of an entire area) receive data = fah (security program setting mode) transmit uart data (transmit data = fah) security program setting security program check blank product check infinite loop ng blank product check blank product check non-blank product non-blank product ok blank product ok blank product check non-blank product ok ok blank product check non-blank product blank product security enable blank product disable security program blank product receive uart data receive data sector erase (block erase) upper 4 bits x 1000h to lower 4 bits x 1000h transmit uart data (checksum of the erased area) upper 4 bits > lower 4 bits transmit uart data (transmit data = 30h) transmit uart data (transmit data = 90h) receive data = 90h (flash memory sum output mode) verify the password (compare the receive data and flash memory data) transmit uart data (checksum) verify the password (compare the receive data and flash memory data) verify the password (compare the receive data and flash memory data) transmit uart data (status of the security program and blank product) transmit uart data (transmit data = fbh) security program check upper 4 bits < lower 4 bits security enabled infinite loop security disabled
15.16 uart timing table 15-19 uart timing-1 (vdd = 4.5 to 5.5 v, fc = 2 to 16 mhz, topr = -10 to 40?c) parameter symbol clock frequency (fc) minimum required time at fc = 2 mhz at fc = 16 mhz time from matching data reception to the echo back cmeb1 approx. 930 465 s 58.1 s time from baud rate modification data reception to the echo back cmeb2 approx. 980 490 s 61.3 s time from operation command reception to the echo back cmeb3 approx. 800 400 s 50 s checksum calculation time cksm approx. 7864500 3.93 s 491.5 s erasure time of an entire flash memory ceall - 30 ms 30 ms erasure time for a sector of a flash memory (in 4-kbyte units) cesec - 15 ms 15 ms table 15-20 uart timing-2 (vdd = 4.5 to 5.5 v, fc = 2 to 16 mhz, topr = -10 to 40?c) parameter symbol clock frequency (fc) minimum required time at fc = 2 mhz at fc = 16 mhz time from the reset release to the acceptance of start bit of rxd pin rxsup 2100 1.05 ms 131.3 ms matching data transmission interval cmtr1 28500 14.2 ms 1.78 ms time from the echo back of matching data to the acceptance of baud rate modification data cmtr2 380 190 s 23.8 s time from the echo back of baud rate modification data to the accept- ance of an operation command cmtr3 650 325 s 40.6 s time from the echo back of operation command to the acceptance of password count storage addresses (upper byte) cmtr4 800 400 s 50 s TMP86FH09AMG page 171 reset pin rxd pin rxsup (5ah) cmeb1 (5ah) cmtr2 (28h) (28h) cmeb2 cmtr3 (30h) (30h) cmeb3 cmtr4 txd pin rxd pin txd pin (5ah) (5ah) (5ah) cmtr1
TMP86FH09AMG 15. serial prom mode 15.16 uart timing page 172
16. input/output circuitry 16.1 control pins the input/output circuitries of the TMP86FH09AMG control pins are shown below. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins r f = 1.55 m (typ.) r o = 0.5 k (typ.) xtin xtout input resonator connecting pins r f = 8 m (typ.) r o = 200 k (typ.) reset input hysteresis input pull-up resistor r in = 220 k (typ.) r = 100 (typ.) test input without pull-down resistor r = 100 (typ.) fix the test pin at low-level in mcu mode. note:the test pin of tmp86fh09/f809/f409ng does not have a pull-down resistor and diode(d1). fix the test pin at low level in mcu mode. TMP86FH09AMG page 173 fs rf r o osc.enable xtin xten xtout vdd vdd r r in r vdd address trap reset watchdog timer reset system clock reset fc rf r o osc.enable xin xout vdd vdd
16.2 input/output ports control pin i/o input/output circuitry remarks p0 i/o sink open drain output or push-pull output hysteresis input high current output(nch) (programmable port option) p1 i/o tri-state i/o hysteresis input p2 i/o sink open drain output hysteresis input p3 i/o tri-state i/o hysteresis input or cmos input TMP86FH09AMG 16. input/output circuitry 16.2 input/output ports page 174 initial "high-z" disable vdd r data output pin input initial "high-z" disable vdd r data output pin input key on wake up input initial "high-z" disable vdd r data output pin input p33,32 initial "high-z" disable vdd r data output pin input p31,30 p37 to 34 analog input analog input initial "high-z" vdd r data output input from output latch pin input initial "high-z" high-z control vdd r pch control data output input from output latch pin input
note:input status on pins set for input mode are read in into the internal circuit. therefore, when using the ports in a maxture of input and output modes, the contents of the output latches for the ports that are set for input mode may be rewritten by execution of bit manipulating instructions. TMP86FH09AMG page 175
TMP86FH09AMG 16. input/output circuitry 16.2 input/output ports page 176
17. electrical characteristics 17.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operation, even for an in- stant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ev- er be exceeded. (vss = 0 v) parameter symbol pins ratings unit supply voltage v dd -0.3 to 6.0 v input voltage v in -0.3 to v dd + 0.3 v output voltage v out1 -0.3 to v dd + 0.3 v output current (per 1 pin) i out1 p0, p1, p3 ports -1.8 ma i out2 p1, p2, p3 ports 3.2 i out3 p0 ports 30 output current (total) i out1 p0, p1, p3 ports -30 i out2 p1, p2, p3 ports 60 i out3 p0 ports 80 power dissipation [topr = 85 c] p d 300 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg -55 to 125 operating temperature topr -40 to 85 TMP86FH09AMG page 177
17.2 operating conditions the operating conditions show the conditions under which the device be used in order for it to operate normal- ly while maintaining its quality. if the device is used outside the range of operating conditions (power supply volt- age, operating temperature range, or ac/dc rated values), it may operate erratically. therefore, when designing your application equipment, always make sure its intended working conditions will not exceed the range of operat- ing conditions. 17.2.1 mcu mode (flash programming or erasing) (v ss = 0 v, topr = -10 to 40c) parameter symbol pins ratings min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input, test v dd 0.25 clock frequency fc xin, xout 1.0 16.0 mhz 17.2.2 mcu mode (except flash programming or erasing) (v ss = 0 v, topr = -40 to 85c) parameter symbol pins ratings min max unit supply voltage v dd fc = 16 mhz normal1, 2 modes idle0, 1, 2 modes 4.5 5.5 v fc = 8 mhz normal1, 2 modes idle0, 1, 2 modes 2.7(note1) fs = 32.768 khz slow1, 2 modes sleep0, 1, 2 modes stop mode input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input,test v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 2.7 to 5.5v 1.0 8.0 mhz v dd = 4.5 to 5.5v 16.0 fs xtin, xtout v dd = 2.7 to 5.5v 30.0 34.0 khz note 1: the operating temperature(topr) must not exceed the range between -20 to 85c under 3.0v. TMP86FH09AMG 17. electrical characteristics 17.2 operating conditions page 178
17.2.3 serial prom mode (v ss = 0 v, topr = -10 to 40 c) parameter symbol pins condition min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high voltage v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low voltage v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input,test v dd 0.25 clock frequency fc xin, xout 2.0 16.0 mhz TMP86FH09AMG page 179
17.3 dc characteristics (v ss = 0 v, topr = -40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input v dd = 5.5 v, v in = 5.5 v/0 v - 0.9 - v input current i in1 test - - 2 a i in2 sink open drain, tri - state port i in3 reset, stop input resistance r in3 reset pull - up v dd = 5.5 v, v in = 0 v 100 220 450 k output leakage current i lo1 sink open drain port v dd = 5.5 v, v out = 5.5 v - - 2 a i lo2 tri - state port v dd = 5.5 v, v out = 5.5 v/0 v - - 2 output high voltage v oh tri - state port v dd = 4.5 v, i oh = -0.7 ma 4.1 - - v output low voltage v ol except xout, p3, p5 v dd = 4.5 v, i ol = 1.6 ma - - 0.4 output low current i ol high current port (p0 port) v dd = 4.5 v, v ol = 1.0 v - 20 - ma supply current in normal1, 2 modes i dd v dd = 5.5 v v in = 5.3 v/0.2 v fc = 16 mhz fs = 32.768 khz when a program operates on flash memory (note4,5) - 10.5 19 ma supply current in idle 0, 1, 2 modes - 4.5 8.5 supply current in slow1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz when a program operates on flash memory (note4,5) - 25 65 a when a program operates on ram - 15 25 supply current in sleep1 mode - 7 15 supply current in sleep0 mode - 5 12 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v - 0.5 10 peak current for slow1 mode (note4,5) i ddp-p v dd = 5.5 v - 10 - ma v dd = 3.0 v - 2 - note 1: typical values show those at topr = 25 c and v dd = 5 v. note 2: input current (i in3 ): the current through pull-up resistor is not included. note 3: the supply currents of slow2 and sleep2 modes are equivalent to those of idle0, idle1 and idle2 modes. note 4: when a program is executing in the flash memory or when data is being read from the flash memory, the flash memo- ry operates in an intermittent manner, causing peak currents in the operation current, as shown in figure 17-1. in this case, the supply current i dd (in normal1, normal2 and slow1 modes) is defined as the sum of the aver- age peak current and mcu current. note 5: when designing the power supply, make sure that peak currents can be supplied. in slow1 mode, the difference be- tween the peak current and the average current becomes large. figure 17-1 intermittent operation of flash memory TMP86FH09AMG 17. electrical characteristics 17.3 dc characteristics page 180 n program coutner (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu current
17.4 ad characteristics (v ss = 0.0 v, 2.7 v v dd 5.5 v, topr = -40 to 85 c) parameter symbol condition min typ. max unit analog input voltage v ain v ss - v dd v non linearity error v dd = 3.0v/5.0 v, v ss = 0.0 v - - 6 lsb zero point error - - 6 full scale error - - 6 total error - - 6 note 1: the total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal con- version line. note 2: conversion time is different in recommended value by power supply voltage. note 3: the voltage to be input on the ain input pin must not exceed the range between v dd and v ss . if a voltage outside this range is input, conversion values will become unstable and conversion values of other channels will also be affected. note 4: the operating temperature(topr) must not exceed the range between -20 to 85c under 3.0v TMP86FH09AMG page 181
17.5 ac characteristics (v ss = 0 v, 4.5 v v dd 5.5 v, topr = -40 to 85c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 modes 0.25 - 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 - 133.3 sleep0, 1, 2 modes high-level clock pulse width t wch for external clock operation (xin input) fc = 16 mhz - 31.25 - ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz - 15.26 - s low-level clock pulse width t wsl (v ss = 0 v, 2.7 v v dd 5.5 v, topr = -40 to 85c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 modes 0.5 - 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 - 133.3 sleep0, 1, 2 modes high-level clock pulse width t wch for external clock operation (xin input) fc = 8 mhz - 62.5 - ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz - 15.26 - s low-level clock pulse width t wsl note 1: the operating temperature(topr) must not exceed the range between -20 to 85c under 3.0v 17.6 flash characteristics 17.6.1 write/erase characteristics (v ss = 0 v) parameter condition min typ. max. unit number of guaranteed writes to flash memory v ss = 0 v, topr = -10 to 40c - - 100 times TMP86FH09AMG 17. electrical characteristics 17.5 ac characteristics page 182
17.7 oscillating conditions xtin xtout (2) low-frequency oscillation xin xout c 1 c 2 (1) high-frequency oscillation c 1 c 2 note 1: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these fac- tors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the de- vice will actually be mounted. note 2: the product numbers and specifications of the resonators supplied by murata manufacturing co., ltd. are subject to change. for up to date information, please refer to the following. http://www.murata.com 17.8 handling precaution - the solderability test conditions are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used the pass criterion of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. TMP86FH09AMG page 183
TMP86FH09AMG 17. electrical characteristics 17.8 handling precaution page 184
18. package dimensions TMP86FH09AMG page 185 p-sop32-380-1.27 unit: mm
TMP86FH09AMG 18. package dimensions page 186
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